Patents by Inventor Kinichi Igarashi

Kinichi Igarashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6384483
    Abstract: A manufacturing method for a semiconductor device, wherein a polyimide-based resin layer is covered with a P-CVD oxide silicon film or the like before it is subjected to degassing process in order to prevent blisters or cracks of a cover film of a semiconductor device which has the polyimide-based resin layer as an interlayer insulating film. This makes it possible to take the semiconductor device out in open air after the degassing process and to prevent the dispersion of reaction products resulting from amidation during the degassing process.
    Type: Grant
    Filed: December 27, 1999
    Date of Patent: May 7, 2002
    Assignee: NEC Corporation
    Inventors: Kinichi Igarashi, Hideaki Sato
  • Patent number: 6323505
    Abstract: First of all, after removing a passivation film on a failure pellet area, a timing failure level of the pellet area is digitized using a tester. Then, a polyimide solution is dropped on the upper semi-circular region of the pellet area. Then, the timing failure level of the pellet after forming the polyimide film is digitized using the tester again. Thereafter, the timing failure value after forming the polyimide film and the timing failure value before forming the polyimide film is compared. Then, based on the comparison results, the region with failure is judged. Then, repeating the step of selectively forming the polyimide film on the region with failure and the step of judging the region with failure, the failure region is identified.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: November 27, 2001
    Assignee: NEC Corporation
    Inventor: Kinichi Igarashi
  • Patent number: 6121160
    Abstract: A manufacturing method for a semiconductor device, wherein a polyimide-based resin layer is covered with a P-CVD oxide silicon film or the like before it is subjected to degassing process in order to prevent blisters or cracks of a cover film of a semiconductor device which has the polyimide-based resin layer as an interlayer insulating film. This makes it possible to take the semiconductor device out in open air after the degassing process and to prevent the dispersion of reaction products resulting from amidation during the degassing process.
    Type: Grant
    Filed: February 6, 1998
    Date of Patent: September 19, 2000
    Assignee: NEC Corporation
    Inventors: Kinichi Igarashi, Hideaki Sato
  • Patent number: 6090634
    Abstract: First of all, after removing a passivation film on a failure pellet area, a timing failure level of the pellet area is digitized using a tester. Then, a polyimide solution is dropped on the upper semi-circular region of the pellet area. Then, the timing failure level of the pellet after forming the polyimide film is digitized using the tester again. Thereafter, the timing failure value after forming the polyimide film and the timing failure value before forming the polyimide film is compared. Then, based on the comparison results, the region with failure is judged. Then, repeating the step of selectively forming the polyimide film on the region with failure and the step of judging the region with failure, the failure region is identified.
    Type: Grant
    Filed: June 25, 1998
    Date of Patent: July 18, 2000
    Assignee: NEC Corporation
    Inventor: Kinichi Igarashi