Patents by Inventor Kinichi Naya

Kinichi Naya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7279792
    Abstract: According to this invention, a semiconductor device has an upper surface on which an external connection electrode is formed and a lower surface which opposes the upper surface and is in a mirror surface state. A roughened region roughened by laser marking is formed at part of the lower surface. The roughened region includes a product information mark of the semiconductor device itself. The product information mark is printed by laser marking. The number, size, shape, and layout position of the roughened regions are decided to make it possible to, when the lower surface is irradiated with light, read the product information from the difference in light reflectance between the roughened region and mirror-finished region.
    Type: Grant
    Filed: May 10, 2004
    Date of Patent: October 9, 2007
    Assignee: Casio Micronics Co., Ltd
    Inventor: Kinichi Naya
  • Publication number: 20050167800
    Abstract: According to this invention, a semiconductor device has an upper surface on which an external connection electrode is formed and a lower surface which opposes the upper surface and is in a mirror surface state. A roughened region roughened by laser marking is formed at part of the lower surface. The roughened region includes a product information mark of the semiconductor device itself. The product information mark is printed by laser marking. The number, size, shape, and layout position of the roughened regions are decided to make it possible to, when the lower surface is irradiated with light, read the product information from the difference in light reflectance between the roughened region and mirror-finished region.
    Type: Application
    Filed: May 10, 2004
    Publication date: August 4, 2005
    Inventor: Kinichi Naya
  • Patent number: 6077765
    Abstract: A method of forming a bump electrode, comprises the steps of preparing an Si-substrate having a plurality of bonding pads, forming a core on a substantially central portion of the bonding pad on the substrate, forming a resist layer around the core, which has a greater plan-view shape than the core and is provided with an opening portion through which that portion of the bonding pad, which is located around the core, is exposed, and coating an electric conduction strip having a uniform thickness on peripheral and upper surfaces of the core and on that portion of the bonding pad, which is located around the core, by a plating method.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: June 20, 2000
    Assignee: Casio Computer Co., Ltd.
    Inventor: Kinichi Naya