Patents by Inventor Kinjiro Kosemura

Kinjiro Kosemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4849368
    Abstract: Disclosed is a method of producing a compound semiconductor device comprising an enhancement-mode transistor and a depletion-mode transistor, each of which has a heterojunction and utilizes a two-dimensional electron gas. The method of producing the device comprises the steps of: forming an undoped GaAs channel layer on a semi-insulating GaAs substrate; forming an N-type AlGaAs electron-supply layer so as to form the heterojunction; forming an N-type GaAs layer; forming an AlGaAs layer; selectively etching the AlGaAs layer to form a recess; performing an etching treatment using an etchant which can etch rapidly GaAs and etch slowly AlGaAs to form simultaneously grooves for gate electrodes of the enhancement-mode transistor and the depletion-mode transistor, the bottoms of the grooves being in the N-type AlGaAs layer and the distance between the bottoms being equal to the thickness of the AlGaAs layer; and forming simultaneously the gate electrodes in the grooves.
    Type: Grant
    Filed: January 21, 1988
    Date of Patent: July 18, 1989
    Assignee: Fujitsu Limited
    Inventors: Yoshimi Yamashita, Kinjiro Kosemura, Hidetoshi Ishiwari, Sumio Yamamoto, Shigeru Kuroda
  • Patent number: 4742379
    Abstract: A compound semiconductor device comprises an enhancement-mode transistor and a depletion-mode transistor, each of which has a heterojunction and utilizes a two-dimensional electron gas. The method of producing the device comprises the steps of: forming an undoped GaAs channel layer on a semi-insulating GaAs substrate; forming an N-type AlGaAs electron-supply layer so as to form the heterojunction; forming an N-type GaAs layer; forming an AlGaAs layer; selectively etching the AlGaAs layer to form a recess; performing an etching treatment using an etchant which can etch rapidly GaAs and etch slowly AlGaAs to form simultaneously grooves for gate electrodes of the enhancement-mode transistor and the depletion-mode transistor, the bottoms of the grooves being in the N-type AlGaAs layer and the distance between the bottoms being equal to the thickness of the AlGaAs layer; and forming simultaneously the gate electrodes in the grooves.
    Type: Grant
    Filed: November 29, 1984
    Date of Patent: May 3, 1988
    Assignee: Fujitsu Limited
    Inventors: Yoshimi Yamashita, Kinjiro Kosemura, Hidetoshi Ishiwari, Sumio Yamamoto, Shigeru Kuroda
  • Patent number: 4578343
    Abstract: A method for producing a field effect type semiconductor device includes the steps of forming a semiconductor active layer on a substrate, forming a resist layer on the semiconductor active layer, exposing a first portion of the resist layer in accordance with a gate electrode pattern, carrying out auxiliary exposure of a second portion near the first portion after or before the exposure of the first portion. The method further includes developing the exposed resist layer, forming a recess in the semiconductor active layer by etching the exposed semiconductor active layer using the resist layer as a mask and forming a gate electrode on the surface of the recess using the resist layer as a mask. This method improves the series resistance between the source electrode and the gate electrode, and also improves the Schottky withstand voltage between the drain electrode and the gate electrode.
    Type: Grant
    Filed: March 28, 1985
    Date of Patent: March 25, 1986
    Assignee: Fujitsu Limited
    Inventors: Kinjiro Kosemura, Yoshimi Yamashita, Noriaki Nakayama, Sumio Yamamoto
  • Patent number: 4427991
    Abstract: A high frequency, hermetically-sealed, semiconductor device with the capability of being cascade-connected with corresponding devices in an advantageous manner. The device consists of a function element which includes at least one semiconductor and other circuit elements necessary for forming a functional amplifier, a DC power circuit for operating the device and high frequency circuits for connecting to corresponding high frequency devices. This device also consists of a metal base substrate, which is used for anchoring the device and mounting other parts of the device thereon, an insulating substrate having a plurality of independent metallized layers used as external contacts and a sealing part for hermetically sealing that part of the insulating substrate which mounts and encloses the function element.
    Type: Grant
    Filed: August 20, 1980
    Date of Patent: January 24, 1984
    Assignee: Fujitsu Limited
    Inventors: Shigeyuki Yamamura, Kinjiro Kosemura, Takao Shima, Norio Hidaka