Patents by Inventor Kinya Daio

Kinya Daio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110307752
    Abstract: A bridging fault which has occurred between clock signal lines in a semiconductor device can be easily detected. A semiconductor device having a plurality of hold circuits and configured such that a scan test can be performed includes a first and a second clock signal lines supplied with normal operational clock signals having at least either frequencies or phases different from each other during normal operation, and a test clock signal controller which switches, during a test, between a state in which a first test clock signal, which is the same as that supplied to the first clock signal line, is supplied to the second clock signal line, and a state in which a second test clock signal, which is inverted or phase-shifted relative to the first test clock signal, is supplied to the second clock signal line.
    Type: Application
    Filed: August 25, 2011
    Publication date: December 15, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Naohiro Fujil, Kinya Daio, Shinichi Yoshimura
  • Patent number: 7925944
    Abstract: In a semiconductor device including an N-line M-stage shift register circuit operated at high speed of, for example, several hundreds MHz. Input circuits input a common test pattern to each of pairs of shift registers in, for example, two lines out of the N lines. A plurality of outputs of the pairs of shift registers in the two lines are compared in comparators, and the comparison results are output. The N-line M-stage shift register circuit and the comparators are operated in synchronization with a clock signal at several hundreds MHz. Hence, even when the circuit scale (area) of the N-line M-stage shift register circuit is increased to involve apparent wiring delay, a defect in the shift register circuit can be detected at an actual speed.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: April 12, 2011
    Assignee: Panasonic Corporation
    Inventors: Masaya Hirose, Takeshi Yamamoto, Kinya Daio, Kenji Watanabe
  • Patent number: 7777512
    Abstract: A semiconductor device 10a includes a normal circuit 11 and a voltage fluctuation detection circuit 12a connected to a power supply 100 in common with the normal circuit 11. The voltage fluctuation detection circuit 12a includes an inverting amplifier 13a, a switching element 14, which is connected between input and output terminals of the inverting amplifier 13a, and a capacitance element 15 connected to the input terminal of the inverting amplifier 13a. After the normal circuit 11 and the switching element 14 are set to an operating state and ON state, respectively, when the switching element 14 is set to OFF state at an arbitrary time, charge corresponding to a power supply voltage Vc0 at that time accumulates in the capacitance element 15.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: August 17, 2010
    Assignee: Panasonic Corporation
    Inventors: Masaya Hirose, Kinya Daio, Hiroki Taniguchi, Kazunari Ikeda, Takahisa Tokushige
  • Publication number: 20090161813
    Abstract: In a semiconductor device including an N-line M-stage shift register circuit operated at high speed of, for example, several hundreds MHz. Input circuits input a common test pattern to each of pairs of shift registers in, for example, two lines out of the N lines. A plurality of outputs of the pairs of shift registers in the two lines are compared in comparators, and the comparison results are output. The N-line M-stage shift register circuit and the comparators are operated in synchronization with a clock signal at several hundreds MHz. Hence, even when the circuit scale (area) of the N-line M-stage shift register circuit is increased to involve apparent wiring delay, a defect in the shift register circuit can be detected at an actual speed.
    Type: Application
    Filed: September 30, 2008
    Publication date: June 25, 2009
    Inventors: Masaya Hirose, Takeshi Yamamoto, Kinya Daio, Kenji Watanabe
  • Patent number: 7498967
    Abstract: The semiconductor device includes: an A/D conversion circuit for A/D-converting an analog input signal and outputting a resultant conversion result; and a computation circuit for performing, in synchronization with the A/D conversion circuit, computation for an updated conversion result without storing the updated conversion result every time the conversion result from the A/D conversion circuit is updated, to determine one computation result from a plurality of conversion results from the A/D conversion circuit and output the computation result.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: March 3, 2009
    Assignee: Panasonic Corporation
    Inventors: Masaya Hirose, Kinya Daio, Tetsuya Oosaka, Tomoko Nobekawa
  • Patent number: 7479908
    Abstract: A semiconductor device includes: an A/D converter; a digital processing circuit for performing processing based on conversion results from the A/D converter; a first test circuit for performing operation processing for checking a nonlinearity error (INLE) of the conversion results from the A/D converter; and a second test circuit for performing operation processing for checking a differential nonlinearity error (DNLE) of the conversion results from the A/D converter. The first test circuit performs only part of the operation processing for checking the nonlinearity error (INLE) of the conversion results from the A/D converter. The second test circuit performs only part of the operation processing for checking the differential nonlinearity error (DNLE) of the conversion results from the A/D converter.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: January 20, 2009
    Assignee: Panasonic Corporation
    Inventors: Masaya Hirose, Kinya Daio, Tetsuya Oosaka
  • Publication number: 20080309378
    Abstract: A semiconductor device 10a includes a normal circuit 11 and a voltage fluctuation detection circuit 12a connected to a power supply 100 in common with the normal circuit 11. The voltage fluctuation detection circuit 12a includes an inverting amplifier 13a, a switching element 14, which is connected between input and output terminals of the inverting amplifier 13a, and a capacitance element 15 connected to the input terminal of the inverting amplifier 13a. After the normal circuit 11 and the switching element 14 are set to an operating state and ON state, respectively, when the switching element 14 is set to OFF state at an arbitrary time, charge corresponding to a power supply voltage Vc0 at that time accumulates in the capacitance element 15.
    Type: Application
    Filed: March 5, 2008
    Publication date: December 18, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO. LTD.
    Inventors: Masaya Hirose, Kinya Daio, Hiroki Taniguchi, Kazunari Ikeda, Takahisa Tokushige
  • Patent number: 7456763
    Abstract: The semiconductor device includes: an A/D conversion circuit; a digital processing circuit for performing processing based on conversion results of the A/D conversion circuit; and an output terminal for testing for outputting the conversion results of the A/D conversion circuit externally. The output of the conversion results from the output terminal for testing is made at timing that is different from timing of other conversion operation of which conversion results are to be outputted later and is longer in cycle than timing of conversion operation.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: November 25, 2008
    Assignee: Panasonic Corporation
    Inventors: Masaya Hirose, Kinya Daio, Tetsuya Oosaka
  • Patent number: 7423472
    Abstract: There is provided a power switching circuit capable of completely breaking a current in an OFF state of a switch connecting power sources even when a voltage difference is generated between the power sources of a plurality of functional blocks separated from each other on an LSI chip. A gate control circuit 1a has a control signal terminal INCNT, a first power imputer terminal IG11, and a second power supply terminal IG12 as input terminals and has a first output terminal OG11 and a second output terminal OG12 as output terminals. The gate of a second P-type transistor P2 is connected to the first output terminal OG11 of the gate control circuit 1a and the gate of a second P-type transistor P2 is connected to the second output terminal OG12 of the gate control circuit 1a, wherein the first P-type transistor P1 and the second P-type transistor P2 are connected in series between a first power source VDD1 and a second power source VDD2 to form a switch section.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: September 9, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaya Hirose, Kinya Daio, Masahiro Gion, Masato Maede, Hisaki Watanabe
  • Publication number: 20080007440
    Abstract: The semiconductor device of the present invention includes: an A/D conversion circuit for A/D-converting an analog input signal and outputting a resultant conversion result; and a computation circuit for performing, in synchronization with the A/D conversion circuit, computation for an updated conversion result without storing the updated conversion result every time the conversion result from the A/D conversion circuit is updated, to determine one computation result from a plurality of conversion results from the A/D conversion circuit and output the computation result.
    Type: Application
    Filed: June 12, 2007
    Publication date: January 10, 2008
    Inventors: Masaya Hirose, Kinya Daio, Tetsuya Oosaka, Tomoko Nobekawa
  • Publication number: 20080007439
    Abstract: A semiconductor device includes: an A/D converter; a digital processing circuit for performing processing based on conversion results from the A/D converter; a first test circuit for performing operation processing for checking a nonlinearity error (INLE) of the conversion results from the A/D converter; and a second test circuit for performing operation processing for checking a differential nonlinearity error (DNLE) of the conversion results from the A/D converter. The first test circuit performs only part of the operation processing for checking the nonlinearity error (INLE) of the conversion results from the A/D converter. The second test circuit performs only part of the operation processing for checking the differential nonlinearity error (DNLE) of the conversion results from the A/D converter.
    Type: Application
    Filed: June 1, 2007
    Publication date: January 10, 2008
    Inventors: Masaya Hirose, Kinya Daio, Tetsuya Oosaka
  • Publication number: 20070164890
    Abstract: The semiconductor device includes: an A/D conversion circuit; a digital processing circuit for performing processing based on conversion results of the A/D conversion circuit; and an output terminal for testing for outputting the conversion results of the A/D conversion circuit externally. The output of the conversion results from the output terminal for testing is made at timing that is different from timing of other conversion operation of which conversion results are to be outputted later and is longer in cycle than timing of conversion operation.
    Type: Application
    Filed: January 3, 2007
    Publication date: July 19, 2007
    Inventors: Masaya Hirose, Kinya Daio, Tetsuya Oosaka
  • Publication number: 20060214722
    Abstract: There is provided a power switching circuit capable of completely breaking a current in an OFF state of a switch connecting power sources even when a voltage difference is generated between the power sources of a plurality of functional blocks separated from each other on an LSI chip. A gate control circuit 1a has a control signal terminal INCNT, a first power imputer terminal IG11, and a second power supply terminal IG12 as input terminals and has a first output terminal OG11 and a second output terminal OG12 as output terminals. The gate of a second P-type transistor P2 is connected to the first output terminal OG11 of the gate control circuit 1a and the gate of a second P-type transistor P2 is connected to the second output terminal OG12 of the gate control circuit 1a, wherein the first P-type transistor P1 and the second P-type transistor P2 are connected in series between a first power source VDD1 and a second power source VDD2 to form a switch section.
    Type: Application
    Filed: March 28, 2006
    Publication date: September 28, 2006
    Inventors: Masaya Hirose, Kinya Daio, Masahiro Gion, Masato Maede, Hisaki Watanabe
  • Publication number: 20060001434
    Abstract: It is an object to comprehensively carry out an actual speed inspection without reducing an operating speed in a normal mode in a scan test for a semiconductor integrated circuit. In order to operate a circuit at a proper frequency in a shift operation, to operate the circuit in an actual operation time in a capture operation, and to effectively implement different duty ratios from each other for a group of circuits having different operating frequency characteristics in the capture operation, the duty ratios of respective clocks are changed in a shift operation cycle immediately before a capture operation cycle and the respective clocks are set to have an equal duty ratio in a capture operation cycle. In that case, an NT signal control circuit for generating an NT signal to specify the switching of the shift operation and the capture operation is provided in a semiconductor integrated circuit to execute an operation in response to the NT signal within one clock cycle.
    Type: Application
    Filed: May 13, 2005
    Publication date: January 5, 2006
    Inventors: Takashi Hiramatsu, Kinya Daio, Akiko Fukuda