Patents by Inventor Kinya Ichikawa

Kinya Ichikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11410975
    Abstract: A method of manufacturing a display device 1 includes: providing a substrate including at least one sub-pixel defined therein and a first wiring disposed for the sub-pixel, and the light-emitting element that includes a first electrode disposed on a lower surface and a second electrode disposed on at least two lateral surfaces intersecting with each other; mounting the light-emitting element on the substrate and electrically connecting the first electrode to the first wiring; forming a resin member covering the at least one light-emitting element, on the substrate, exposing a portion of the second electrode from an upper surface of the resin member by removing an upper portion of the resin member; and forming a second wiring with a mesh shape on the resin member such that a portion of the second wiring is disposed on the light-emitting element to electrically connect the second wiring to the second electrode.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: August 9, 2022
    Assignee: NICHIA CORPORATION
    Inventors: Kinya Ichikawa, Katsuyoshi Kadan, Masahiko Sano, Ryohei Hirose, Hiroshi Yoneda
  • Patent number: 11362246
    Abstract: A method of manufacturing a display device 1 includes: providing a substrate including sub-pixel defined therein and a first wiring disposed for the sub-pixel, and light-emitting element having a lower surface and a lateral surface and including a first electrode disposed on the lower surface, and a second electrode disposed on the lateral surface; mounting the light-emitting element and electrically connecting the first electrode to the first wiring; forming a resin member on the substrate and covering the light-emitting element; exposing an upper portion of the light-emitting element from an upper surface of the resin member such that the second electrode is partially exposed by removing an upper portion of the resin member; and forming a second wiring on the upper surface of the resin member excluding a portion of the light-emitting element exposed from the resin member and electrically connecting the second wiring to the second electrode.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: June 14, 2022
    Assignee: NICHIA CORPORATION
    Inventors: Kinya Ichikawa, Katsuyoshi Kadan, Masahiko Sano, Ryohei Hirose, Hiroshi Yoneda
  • Publication number: 20200266176
    Abstract: A method of manufacturing a display device 1 includes: providing a substrate including at least one sub-pixel defined therein and a first wiring disposed for the sub-pixel, and the light-emitting element that includes a first electrode disposed on a lower surface and a second electrode disposed on at least two lateral surfaces intersecting with each other; mounting the light-emitting element on the substrate and electrically connecting the first electrode to the first wiring; forming a resin member covering the at least one light-emitting element, on the substrate, exposing a portion of the second electrode from an upper surface of the resin member by removing an upper portion of the resin member; and forming a second wiring with a mesh shape on the resin member such that a portion of the second wiring is disposed on the light-emitting element to electrically connect the second wiring to the second electrode.
    Type: Application
    Filed: February 20, 2020
    Publication date: August 20, 2020
    Inventors: Kinya Ichikawa, Katsuyoshi Kadan, Masahiko Sano, Ryohei Hirose, Hiroshi Yoneda
  • Publication number: 20200266326
    Abstract: A method of manufacturing a display device 1 includes: providing a substrate including sub-pixel defined therein and a first wiring disposed for the sub-pixel, and light-emitting element having a lower surface and a lateral surface and including a first electrode disposed on the lower surface, and a second electrode disposed on the lateral surface; mounting the light-emitting element and electrically connecting the first electrode to the first wiring; forming a resin member on the substrate and covering the light-emitting element; exposing an upper portion of the light-emitting element from an upper surface of the resin member such that the second electrode is partially exposed by removing an upper portion of the resin member; and forming a second wiring on the upper surface of the resin member excluding a portion of the light-emitting element exposed from the resin member and electrically connecting the second wiring to the second electrode.
    Type: Application
    Filed: February 20, 2020
    Publication date: August 20, 2020
    Inventors: Kinya Ichikawa, Katsuyoshi Kadan, Masahiko Sano, Ryohei Hirose, Hiroshi Yoneda
  • Patent number: 9741664
    Abstract: Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a technique can include creating a multidie substrate, printing an interconnect bridge on the multidie substrate, electrically coupling a first die to a second die by coupling the first and second dies through the interconnect bridge.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: August 22, 2017
    Assignee: Intel Corporation
    Inventors: Chia-Pin Chiu, Kinya Ichikawa, Robert L. Sankman
  • Patent number: 9685388
    Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: June 20, 2017
    Assignee: Intel Corporation
    Inventors: Yoshihiro Tomita, Jiro Kubota, Omkar G. Karhade, Shawna M. Liff, Kinya Ichikawa, Nitin A. Deshpande
  • Publication number: 20170040238
    Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.
    Type: Application
    Filed: October 18, 2016
    Publication date: February 9, 2017
    Applicant: Intel Corporation
    Inventors: Yoshihiro Tomita, Jiro Kubota, Omkar G. Karhade, Shawna M. Liff, Kinya Ichikawa, Nitin A. Deshpande
  • Patent number: 9502368
    Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: November 22, 2016
    Assignee: Intel Corporation
    Inventors: Yoshihiro Tomita, Jiro Kubota, Omkar G. Karhade, Shawna M. Liff, Kinya Ichikawa, Nitin A. Deshpande
  • Publication number: 20160247763
    Abstract: Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a technique can include creating a multidie substrate, printing an interconnect bridge on the multidie substrate, electrically coupling a first die to a second die by coupling the first and second dies through the interconnect bridge.
    Type: Application
    Filed: May 5, 2016
    Publication date: August 25, 2016
    Inventors: Chia-Pin Chiu, Kinya Ichikawa, Robert L. Sankman
  • Publication number: 20160172323
    Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.
    Type: Application
    Filed: December 16, 2014
    Publication date: June 16, 2016
    Applicant: Intel Corporation
    Inventors: YOSHIHIRO TOMITA, JIRO KUBOTA, OMKAR G. KARHADE, SHAWNA M. LIFF, KINYA ICHIKAWA, NITIN A. DESHPANDE
  • Patent number: 9349703
    Abstract: Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a technique can include creating a multidie substrate, printing an interconnect bridge on the multidie substrate, electrically coupling a first die to a second die by coupling the first and second dies through the interconnect bridge.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: May 24, 2016
    Assignee: Intel Corporation
    Inventors: Chia-Pin Chiu, Kinya Ichikawa, Robert L. Sankman
  • Patent number: 9263329
    Abstract: A method of fabricating an electronic package. The method includes filling a mold with an electric conductor to form a number of electrical interconnects within the mold. The mold includes openings that are filled with several electric conductors to form a number of electrical interconnects. The method of fabricating an electronic package further includes attaching the mold to a substrate such that the electrical interconnects engage electrical contacts on the substrate. The method of fabricating an electronic package may further include forming conductive pads on the electrical insulator that engage the electrical interconnects and attaching a die to the substrate such that the die is electrically connected to at least some of the electrical interconnects.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: February 16, 2016
    Assignee: Intel Corporation
    Inventors: Chia-Pin Chiu, Kinya Ichikawa, Yoshihiro Tomita, Robert L. Sankman, Eric Li
  • Publication number: 20150270169
    Abstract: A method of fabricating an electronic package. The method includes filling a mold with an electric conductor to form a number of electrical interconnects within the mold. The mold includes openings that are filled with several electric conductors to form a number of electrical interconnects. The method of fabricating an electronic package further includes attaching the mold to a substrate such that the electrical interconnects engage electrical contacts on the substrate. The method of fabricating an electronic package may further include forming conductive pads on the electrical insulator that engage the electrical interconnects and attaching a die to the substrate such that the die is electrically connected to at least some of the electrical interconnects.
    Type: Application
    Filed: March 19, 2014
    Publication date: September 24, 2015
    Inventors: Chia-Pin Chiu, Kinya Ichikawa, Yoshihiro Tomita, Robert L. Sankman, Eric Li
  • Publication number: 20150084210
    Abstract: Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a technique can include creating a multidie substrate, printing an interconnect bridge on the multidie substrate, electrically coupling a first die to a second die by coupling the first and second dies through the interconnect bridge.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 26, 2015
    Inventors: Chia-Pin Chiu, Kinya Ichikawa, Robert L. Sankman
  • Publication number: 20120112336
    Abstract: An encapsulated die (100, 401) comprises a substrate (110, 510) having a first surface (111), an opposing second surface (112), and intervening side surfaces (113), with active devices located at the first surface of the substrate. The active devices are connected by a plurality of electrically conductive layers (120, 520) that are separated from each other by a plurality of electrically insulating layers (125, 525). A protective cap (130, 530) is located over the first surface of the substrate contains an interconnect structure (140) exposed at a surface (131) thereof. In another embodiment, a microelectronic package (200) comprises a package substrate (250) with an encapsulated die (100) such as was described above embedded therein.
    Type: Application
    Filed: November 5, 2010
    Publication date: May 10, 2012
    Inventors: John S. Guzek, Robert L. Sankman, Kinya Ichikawa, Yoshihiro Tomita, Jiro Kubota
  • Patent number: 8110920
    Abstract: A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: February 7, 2012
    Assignee: Intel Corporation
    Inventors: Sriram Dattaguru, Lesley A. Polka Wood, Yoshihiro Tomita, Kinya Ichikawa, Robert L. Sankman
  • Publication number: 20100309704
    Abstract: A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.
    Type: Application
    Filed: June 5, 2009
    Publication date: December 9, 2010
    Inventors: Sriram Dattaguru, Lesley A. Polka Wood, Yoshihiro Tomita, Kinya Ichikawa, Robert L. Sankman
  • Patent number: 7495330
    Abstract: In one embodiment, a stack is assembled comprising a first integrated circuit package, and a substrate connector which connects the integrated circuit package to a circuit board. In one embodiment, the substrate connector includes an interposer substrate and a patch substrate bonded to the interposer substrate. Each substrate includes columnar conductors extending through the substrate to connect to another layer. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: February 24, 2009
    Assignee: Intel Corporation
    Inventor: Kinya Ichikawa
  • Patent number: 7345361
    Abstract: A system may include an integrated circuit die, an integrated circuit package coupled to the integrated circuit die, mold compound in contact with the integrated circuit die and the integrated circuit package, and an interconnect coupled to the integrated circuit package. A first portion of the interconnect may be in contact with the mold compound, a second portion of the interconnect might not contact the mold compound, and a third portion of the interconnect may be in contact with the integrated circuit package.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: March 18, 2008
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Kinya Ichikawa, Terry L. Sterrett, Johanna Swan
  • Publication number: 20070231475
    Abstract: In some embodiments, conductor structure on dielectric material is presented. In this regard, a substrate in introduced having a conductive paste layer to adhere to dielectric material without a micro-anchor. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 4, 2007
    Inventors: Tadanori Shimoto, Kinya Ichikawa