Patents by Inventor Kinya Ichikawa
Kinya Ichikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11410975Abstract: A method of manufacturing a display device 1 includes: providing a substrate including at least one sub-pixel defined therein and a first wiring disposed for the sub-pixel, and the light-emitting element that includes a first electrode disposed on a lower surface and a second electrode disposed on at least two lateral surfaces intersecting with each other; mounting the light-emitting element on the substrate and electrically connecting the first electrode to the first wiring; forming a resin member covering the at least one light-emitting element, on the substrate, exposing a portion of the second electrode from an upper surface of the resin member by removing an upper portion of the resin member; and forming a second wiring with a mesh shape on the resin member such that a portion of the second wiring is disposed on the light-emitting element to electrically connect the second wiring to the second electrode.Type: GrantFiled: February 20, 2020Date of Patent: August 9, 2022Assignee: NICHIA CORPORATIONInventors: Kinya Ichikawa, Katsuyoshi Kadan, Masahiko Sano, Ryohei Hirose, Hiroshi Yoneda
-
Patent number: 11362246Abstract: A method of manufacturing a display device 1 includes: providing a substrate including sub-pixel defined therein and a first wiring disposed for the sub-pixel, and light-emitting element having a lower surface and a lateral surface and including a first electrode disposed on the lower surface, and a second electrode disposed on the lateral surface; mounting the light-emitting element and electrically connecting the first electrode to the first wiring; forming a resin member on the substrate and covering the light-emitting element; exposing an upper portion of the light-emitting element from an upper surface of the resin member such that the second electrode is partially exposed by removing an upper portion of the resin member; and forming a second wiring on the upper surface of the resin member excluding a portion of the light-emitting element exposed from the resin member and electrically connecting the second wiring to the second electrode.Type: GrantFiled: February 20, 2020Date of Patent: June 14, 2022Assignee: NICHIA CORPORATIONInventors: Kinya Ichikawa, Katsuyoshi Kadan, Masahiko Sano, Ryohei Hirose, Hiroshi Yoneda
-
Publication number: 20200266176Abstract: A method of manufacturing a display device 1 includes: providing a substrate including at least one sub-pixel defined therein and a first wiring disposed for the sub-pixel, and the light-emitting element that includes a first electrode disposed on a lower surface and a second electrode disposed on at least two lateral surfaces intersecting with each other; mounting the light-emitting element on the substrate and electrically connecting the first electrode to the first wiring; forming a resin member covering the at least one light-emitting element, on the substrate, exposing a portion of the second electrode from an upper surface of the resin member by removing an upper portion of the resin member; and forming a second wiring with a mesh shape on the resin member such that a portion of the second wiring is disposed on the light-emitting element to electrically connect the second wiring to the second electrode.Type: ApplicationFiled: February 20, 2020Publication date: August 20, 2020Inventors: Kinya Ichikawa, Katsuyoshi Kadan, Masahiko Sano, Ryohei Hirose, Hiroshi Yoneda
-
Publication number: 20200266326Abstract: A method of manufacturing a display device 1 includes: providing a substrate including sub-pixel defined therein and a first wiring disposed for the sub-pixel, and light-emitting element having a lower surface and a lateral surface and including a first electrode disposed on the lower surface, and a second electrode disposed on the lateral surface; mounting the light-emitting element and electrically connecting the first electrode to the first wiring; forming a resin member on the substrate and covering the light-emitting element; exposing an upper portion of the light-emitting element from an upper surface of the resin member such that the second electrode is partially exposed by removing an upper portion of the resin member; and forming a second wiring on the upper surface of the resin member excluding a portion of the light-emitting element exposed from the resin member and electrically connecting the second wiring to the second electrode.Type: ApplicationFiled: February 20, 2020Publication date: August 20, 2020Inventors: Kinya Ichikawa, Katsuyoshi Kadan, Masahiko Sano, Ryohei Hirose, Hiroshi Yoneda
-
Patent number: 9741664Abstract: Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a technique can include creating a multidie substrate, printing an interconnect bridge on the multidie substrate, electrically coupling a first die to a second die by coupling the first and second dies through the interconnect bridge.Type: GrantFiled: May 5, 2016Date of Patent: August 22, 2017Assignee: Intel CorporationInventors: Chia-Pin Chiu, Kinya Ichikawa, Robert L. Sankman
-
Patent number: 9685388Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.Type: GrantFiled: October 18, 2016Date of Patent: June 20, 2017Assignee: Intel CorporationInventors: Yoshihiro Tomita, Jiro Kubota, Omkar G. Karhade, Shawna M. Liff, Kinya Ichikawa, Nitin A. Deshpande
-
Publication number: 20170040238Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.Type: ApplicationFiled: October 18, 2016Publication date: February 9, 2017Applicant: Intel CorporationInventors: Yoshihiro Tomita, Jiro Kubota, Omkar G. Karhade, Shawna M. Liff, Kinya Ichikawa, Nitin A. Deshpande
-
Patent number: 9502368Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.Type: GrantFiled: December 16, 2014Date of Patent: November 22, 2016Assignee: Intel CorporationInventors: Yoshihiro Tomita, Jiro Kubota, Omkar G. Karhade, Shawna M. Liff, Kinya Ichikawa, Nitin A. Deshpande
-
Publication number: 20160247763Abstract: Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a technique can include creating a multidie substrate, printing an interconnect bridge on the multidie substrate, electrically coupling a first die to a second die by coupling the first and second dies through the interconnect bridge.Type: ApplicationFiled: May 5, 2016Publication date: August 25, 2016Inventors: Chia-Pin Chiu, Kinya Ichikawa, Robert L. Sankman
-
Publication number: 20160172323Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.Type: ApplicationFiled: December 16, 2014Publication date: June 16, 2016Applicant: Intel CorporationInventors: YOSHIHIRO TOMITA, JIRO KUBOTA, OMKAR G. KARHADE, SHAWNA M. LIFF, KINYA ICHIKAWA, NITIN A. DESHPANDE
-
Patent number: 9349703Abstract: Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a technique can include creating a multidie substrate, printing an interconnect bridge on the multidie substrate, electrically coupling a first die to a second die by coupling the first and second dies through the interconnect bridge.Type: GrantFiled: September 25, 2013Date of Patent: May 24, 2016Assignee: Intel CorporationInventors: Chia-Pin Chiu, Kinya Ichikawa, Robert L. Sankman
-
Patent number: 9263329Abstract: A method of fabricating an electronic package. The method includes filling a mold with an electric conductor to form a number of electrical interconnects within the mold. The mold includes openings that are filled with several electric conductors to form a number of electrical interconnects. The method of fabricating an electronic package further includes attaching the mold to a substrate such that the electrical interconnects engage electrical contacts on the substrate. The method of fabricating an electronic package may further include forming conductive pads on the electrical insulator that engage the electrical interconnects and attaching a die to the substrate such that the die is electrically connected to at least some of the electrical interconnects.Type: GrantFiled: March 19, 2014Date of Patent: February 16, 2016Assignee: Intel CorporationInventors: Chia-Pin Chiu, Kinya Ichikawa, Yoshihiro Tomita, Robert L. Sankman, Eric Li
-
Publication number: 20150270169Abstract: A method of fabricating an electronic package. The method includes filling a mold with an electric conductor to form a number of electrical interconnects within the mold. The mold includes openings that are filled with several electric conductors to form a number of electrical interconnects. The method of fabricating an electronic package further includes attaching the mold to a substrate such that the electrical interconnects engage electrical contacts on the substrate. The method of fabricating an electronic package may further include forming conductive pads on the electrical insulator that engage the electrical interconnects and attaching a die to the substrate such that the die is electrically connected to at least some of the electrical interconnects.Type: ApplicationFiled: March 19, 2014Publication date: September 24, 2015Inventors: Chia-Pin Chiu, Kinya Ichikawa, Yoshihiro Tomita, Robert L. Sankman, Eric Li
-
Publication number: 20150084210Abstract: Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a technique can include creating a multidie substrate, printing an interconnect bridge on the multidie substrate, electrically coupling a first die to a second die by coupling the first and second dies through the interconnect bridge.Type: ApplicationFiled: September 25, 2013Publication date: March 26, 2015Inventors: Chia-Pin Chiu, Kinya Ichikawa, Robert L. Sankman
-
Publication number: 20120112336Abstract: An encapsulated die (100, 401) comprises a substrate (110, 510) having a first surface (111), an opposing second surface (112), and intervening side surfaces (113), with active devices located at the first surface of the substrate. The active devices are connected by a plurality of electrically conductive layers (120, 520) that are separated from each other by a plurality of electrically insulating layers (125, 525). A protective cap (130, 530) is located over the first surface of the substrate contains an interconnect structure (140) exposed at a surface (131) thereof. In another embodiment, a microelectronic package (200) comprises a package substrate (250) with an encapsulated die (100) such as was described above embedded therein.Type: ApplicationFiled: November 5, 2010Publication date: May 10, 2012Inventors: John S. Guzek, Robert L. Sankman, Kinya Ichikawa, Yoshihiro Tomita, Jiro Kubota
-
Patent number: 8110920Abstract: A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.Type: GrantFiled: June 5, 2009Date of Patent: February 7, 2012Assignee: Intel CorporationInventors: Sriram Dattaguru, Lesley A. Polka Wood, Yoshihiro Tomita, Kinya Ichikawa, Robert L. Sankman
-
Publication number: 20100309704Abstract: A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.Type: ApplicationFiled: June 5, 2009Publication date: December 9, 2010Inventors: Sriram Dattaguru, Lesley A. Polka Wood, Yoshihiro Tomita, Kinya Ichikawa, Robert L. Sankman
-
Patent number: 7495330Abstract: In one embodiment, a stack is assembled comprising a first integrated circuit package, and a substrate connector which connects the integrated circuit package to a circuit board. In one embodiment, the substrate connector includes an interposer substrate and a patch substrate bonded to the interposer substrate. Each substrate includes columnar conductors extending through the substrate to connect to another layer. Other embodiments are described and claimed.Type: GrantFiled: June 30, 2005Date of Patent: February 24, 2009Assignee: Intel CorporationInventor: Kinya Ichikawa
-
Patent number: 7345361Abstract: A system may include an integrated circuit die, an integrated circuit package coupled to the integrated circuit die, mold compound in contact with the integrated circuit die and the integrated circuit package, and an interconnect coupled to the integrated circuit package. A first portion of the interconnect may be in contact with the mold compound, a second portion of the interconnect might not contact the mold compound, and a third portion of the interconnect may be in contact with the integrated circuit package.Type: GrantFiled: December 4, 2003Date of Patent: March 18, 2008Assignee: Intel CorporationInventors: Debendra Mallik, Kinya Ichikawa, Terry L. Sterrett, Johanna Swan
-
Publication number: 20070231475Abstract: In some embodiments, conductor structure on dielectric material is presented. In this regard, a substrate in introduced having a conductive paste layer to adhere to dielectric material without a micro-anchor. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: March 31, 2006Publication date: October 4, 2007Inventors: Tadanori Shimoto, Kinya Ichikawa