Abstract: To minimize skew and jitter imposed upon signals communicated along a printed circuit signal path a termination circuit is formed proximate the sink or receiving element of the signals. The termination circuit can be resistive, coupling the signal path to a supply power and to a ground potential.

Abstract: A clock generator produces a plurality of clock signals from a master clock and a delayed clock version of the master clock by applying a division of the delayed version of the master clock to the data input of a flip-flop and clocking the flip-flop with the master clock. A number of plurality of clock signals are produced by applying the output of the flip-flop to the data input of an array of second flip-flops--one flip-flop of the array for each of the number of clock signals--that are clocked by the delayed version of the master clock.

Abstract: A master clock signal, used to operate the clock devices (e.g., flip flops) formed on an integrated circuit chip, includes first and second clock paths. The first clock path is a linear trunk having laterally extending tributaries. The clock trunk is driven, through buffer circuits, at both ends with the master clock, and the internal devices coupled to the tributaries to receive the clock signal. The second path comprises a closed loop formed proximate the periphery of the integrated circuit chip. Clock buffer circuitry receives the master clock signal and apply that master clock signal to two points on the closed loop path. The closed loop path is used to communicate the master clock to only the input/output devices, i.e., those that receive data and/or informational signals from an external source, or that communicate such signals to a destination external to the integrated circuit.

Abstract: A clock generator system for producing a number of multiple frequency digital clock signals for distribution to a number of synchronous, clocked devices, include two separate, substantially identically structured clock generator units that operate in lock-step unison. The digital clock signal outputs of one of the generator units are distributed to the synchronous, clocked devices and to an error detection circuit, that also receives the digital clock signals from other clock generator unit for comparison with one another. In the event an error is detected, the error detection circuit will produce an error signal to halt operation of the system with which the clock generator system is used, and reset the clock generator.

Abstract: A clock generator system for producing a number of multiple frequency digital clock signals for distribution to a number of synchronous, clocked devices, include two separate, substantially identically structured clock generator units that operate in lock-step unison. The digital clock signal outputs of one of the generator units are distributed to the synchronous, clocked devices and to an error detection circuit, that also receives the digital clock signals from other clock generator unit for comparison with one another. In the event an error is detected, the error detection circuit will produce an error signal to halt operation of the system with which the clock generator system is used, and reset the clock generator.