Patents by Inventor Kio Yamamoto

Kio Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hermetic sealing of wafer scale integrated wafer
    Patent number: 5150196
    Abstract: A hermetically sealed integrated wafer wherein the integrated wafer is sandwiched between a support layer and expansion buffering layer. The expansion buffering layer includes a centrally-located opening through which integrated circuits located on the wafer may extend. A sealing ring and cover plate are bonded to the expansion buffering layer to provide hermetic sealing of integrated circuits or other electronic elements located on the wafer.
    Type: Grant
    Filed: July 17, 1989
    Date of Patent: September 22, 1992
    Assignee: Hughes Aircraft Company
    Inventors: Kio Yamamoto, Stewart O. Fong