Abstract: A method and apparatus to provide high speed voice/data switching with efficient utilization of available bandwidth and minimal switching delay. More specifically, this invention uses shift registers at each crosspoint of a switching matrix. In each slot position of the register, there is a bit representing the status of an associated crosspoint during a particular time slot. Each slot position of the register represents a different time slot. The status of the crosspoint changes in accordance with the bit that is in a designated slot position during each time slot. During each time slot, at most one bit of data/voice is then transmitted through any given closed crosspoint.