Patents by Inventor Kiran B. Doreswamy

Kiran B. Doreswamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110239195
    Abstract: Dependence-based software builds are described. In embodiments, authored source code is received as inputs to a computer device to develop a buildable unit of a software build project. The software build project includes multiple buildable units that can be allocated for independent development among multiple developers, such as at computer devices local to each developer. At the computer device, dependent buildable units are identified that have a dependency relationship with the buildable unit for execution. The authored source code of the buildable unit is then validated to determine that the buildable unit executes with the dependent buildable units for error-free execution before the buildable unit is subsequently provided to a software build service that compiles the multiple buildable units to generate the software build project.
    Type: Application
    Filed: March 25, 2010
    Publication date: September 29, 2011
    Applicant: MICROSOFT CORPORATION
    Inventors: Zheng Lin, Michael L. Rowand, JR., Jonathan M. Class, Kiran B. Doreswamy, Om K. Sharma
  • Patent number: 7149675
    Abstract: A method for automatically mapping state elements between a first circuit and a second circuit is described. The method proceeds by comparing, in a structural phase, structural features of state elements in the first circuit to structural features of state elements in the second circuit for equivalence. Mappings between state elements of the first circuit and the second circuit are determined based on the comparison of structural features. “Don't care” input conditions are then accounted for prior to determination of functional features. During an inversion detection phase, the polarity of the mappings found in the prior structural phase are determined. A functional phase follows in which the functionality of state elements in the first circuit are compared to the functionality of state elements in the second circuit for equivalence using a three-valued random simulation and further mappings are determined based upon the functional comparison.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: December 12, 2006
    Assignee: Intel Corporation
    Inventors: Yatin V. Hoskote, Kiran B. Doreswamy
  • Patent number: 6467058
    Abstract: A method of generating a vector set, said vector set being used for testing sequential circuits. The method comprises selecting a plurality of fault models, identifying a fault list each for each of said plurality of fault models, identifying a vector set each for each of said fault lists, selecting a tolerance limit each for each of said fault lists, thereby each fault model having an associated fault list, an associated vector set and an associated tolerance limit, compacting each of said vector set such that the compacted vector set identifies all the faults in the associated fault list or a drop in fault list coverage is within the associated tolerance limit; and creating a vector set by combining all vector sets compacted. A system and a computer program product for testing circuits with a compacted vector set where the compacted vector set is created by dropping faults based on a tolerance limit.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: October 15, 2002
    Assignee: NEC USA, Inc.
    Inventors: Srimat T. Chakradhar, Surendra K. Bommu, Kiran B. Doreswamy
  • Publication number: 20020144215
    Abstract: A method for automatically mapping state elements between a first circuit and a second circuit is described. The method proceeds by comparing, in a structural phase, structural features of state elements in the first circuit to structural features of state elements in the second circuit for equivalence. Mappings between state elements of the first circuit and the second circuit are determined based on the comparison of structural features. “Don't care” input conditions are then accounted for prior to determination of functional features. During an inversion detection phase, the polarity of the mappings found in the prior structural phase are determined. A functional phase follows in which the functionality of state elements in the first circuit are compared to the functionality of state elements in the second circuit for equivalence using a three-valued random simulation and further mappings are determined based upon the functional comparison.
    Type: Application
    Filed: March 9, 2001
    Publication date: October 3, 2002
    Inventors: Yatin V. Hoskote, Kiran B. Doreswamy
  • Patent number: 6378096
    Abstract: A method of solving a test generation problem for sequential circuits is disclosed. The method comprises recursively dividing an original test generation problem into smaller problems, wherein said sub-problems may be dependent while one or more of said dependent sub-problems may have solution-specific independence, finding solutions for said sub-problems, reusing solutions for dependent sub-problems, whenever the dependent sub-problems enjoy solution-specific independence; and identifying a minimal subset of conflicting objectives if a sub-problem that has to be solved to achieve multiple objectives has no solution. A test generation system comprising a computer, said computer having a cpu and memory, said memory comprising instructions capable of implementing components of said system.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: April 23, 2002
    Assignee: NEC USA, Inc.
    Inventors: Srimat T. Chakradhar, Kiran B. Doreswamy, Surendra K. Bommu, Xijiang Lin
  • Patent number: 6223316
    Abstract: A two phase vector restoration technique which extracts a minimal subsequence from a sequence that detects a chosen set of faults is provided. The disclosed vector restoration technique is useful in static compaction of test sequences and in fault diagnosis. An accelerated two phase vector restoration that provides further improvement is also provided. The present invention is a significant improvement over the state of the art in the following ways: (1) a sequence of length n can be restored with only O(n log2n) simulations while known approaches require simulation of O(n2) vectors, (2) a two-step restoration process is used that makes vector restoration practical for large designs, and (3) restoration process for several faults is overlapped to provide significant acceleration in vector restoration. The described vector restoration technique has been integrated into a static test sequence compaction system.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: April 24, 2001
    Assignee: NEC USA, Inc.
    Inventors: Surendra K. Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy
  • Patent number: 5987636
    Abstract: A technique for static compaction of test sequences is described. The method for static compaction according to the present invention includes two key features: (1) two-phase vector restoration, and (2) identification, pruning, and re-ordering of segments. Segments partition the compaction problem into sub-problems. Segments are identified, dynamically pruned and re-ordered to achieve further compaction and speed up.
    Type: Grant
    Filed: August 18, 1998
    Date of Patent: November 16, 1999
    Assignee: NEC USA, Inc.
    Inventors: Surendra K. Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy