Abstract: A multi-protocol communication circuit, for example, a serializer-deserializer (SerDes) circuit for communicating between an internal logic circuit and an external link includes a select terminal configured to accept a select signal representing a plurality of mode select signal. A SerDes core is coupled to the select terminal and configured to transmit outbound data conforming with a first communication protocol in response to a first mode select signal and conforming with a second communication protocol in response to a second mode select signal. The SerDes core is also configured to receive inbound data respective to a first communication protocol in response to a first mode select signal and respective to a second communication protocol in response to a second mode select signal. Advantages of the invention include the ability to provide high bandwidth communications between integrated circuits that employ different SerDes protocols.

Abstract: A method and apparatus for auto-tuning memory is provided. Memory on a computer system comprises at least one shared memory area and at least one private memory area. Addresses in the shared memory area are accessible to multiple processes. Addresses in the private memory area are dedicated to individual processes. Initially, a division in the amount of memory is established between the shared and private memory areas. Subsequently, a new division is determined. Consequently, memory from one memory area is “given” to the other memory area. In one approach, such sharing is achieved by causing the shared and private memory areas to be physically separate from each other both before and after a change in the division. The division of the amount of memory may be changed to a new division by deallocating memory from one of the memory areas and allocating that memory to the other of the memory areas.

Abstract: Dependence-based software builds are described. In embodiments, authored source code is received as inputs to a computer device to develop a buildable unit of a software build project. The software build project includes multiple buildable units that can be allocated for independent development among multiple developers, such as at computer devices local to each developer. At the computer device, dependent buildable units are identified that have a dependency relationship with the buildable unit for execution. The authored source code of the buildable unit is then validated to determine that the buildable unit executes with the dependent buildable units for error-free execution before the buildable unit is subsequently provided to a software build service that compiles the multiple buildable units to generate the software build project.

Abstract: The present invention relates to a stable pyrithione salt polyol dispersion containing a pyrithione salt(s) in particulate form, a polyol and a stabilizer such as a rheological additive. The dispersion can be incorporated into existing polyurethane formulations without additional formula adjustment. Polyurethane foams produced from the composition containing pyrithione salt polyol dispersion of the present invention have more open cell structures, than those produced with a typical commercially available pyrithione salt thus providing a soft comfortable feeling.

Abstract: Techniques are provided for using an intermediate cache to provide some of the items involved in a scan operation, while other items involved in the scan operation are provided from primary storage. Techniques are also provided for determining whether to service an I/O request for an item with a copy of the item that resides in the intermediate cache based on factors such as a) an identity of the user for whom the I/O request was submitted, b) an identity of a service that submitted the I/O request, c) an indication of a consumer group to which the I/O request maps, d) whether the I/O request is associated with an offloaded filter provided by the database server to the storage system, or e) whether the intermediate cache is overloaded. Techniques are also provided for determining whether to store items in an intermediate cache in response to the items being retrieved, based on logical characteristics associated with the requests that retrieve the items.

Abstract: A partial reverse key index is described, which allows distributed contention as resources vie to insert data into an index as well as allows range scans to be performed on the index. To do so, before an index entry for a key value is inserted into an index, the key value is transformed using a transformation operation that affects a subset of the order of the key value. The index entry is then inserted based on the transformed key value. Because the transformation operation affects the order of the key value, the transformed values associated with two consecutive key values will not necessarily be consecutive. Therefore, the index entries associated with the consecutive key values may be inserted into unrelated portions of the index.

Abstract: A method and apparatus for auto-tuning memory is provided. Memory on a computer system comprises at least one shared memory area and at least one private memory area. Addresses in the shared memory area are accessible to multiple processes. Addresses in the private memory area are dedicated to individual processes. Initially, a division in the amount of memory is established between the shared and private memory areas. Subsequently, a new division is determined. Consequently, memory from one memory area is “given” to the other memory area. In one approach, such sharing is achieved by causing the shared and private memory areas to be physically separate from each other both before and after a change in the division. The division of the amount of memory may be changed to a new division by deallocating memory from one of the memory areas and allocating that memory to the other of the memory areas.

Abstract: The present invention relates to the color stabilization of hydroquinone hydroxyethyl ethers by phosphite compounds containing the bis-cyclic structure of spiro phosphites, both rings being attached to the same tertiary carbon atom in the phosphite molecule.

Abstract: A method for automatically mapping state elements between a first circuit and a second circuit is described. The method proceeds by comparing, in a structural phase, structural features of state elements in the first circuit to structural features of state elements in the second circuit for equivalence. Mappings between state elements of the first circuit and the second circuit are determined based on the comparison of structural features. “Don't care” input conditions are then accounted for prior to determination of functional features. During an inversion detection phase, the polarity of the mappings found in the prior structural phase are determined. A functional phase follows in which the functionality of state elements in the first circuit are compared to the functionality of state elements in the second circuit for equivalence using a three-valued random simulation and further mappings are determined based upon the functional comparison.

Abstract: The present invention relates to the color stabilization of hydroquinone hydroxyethyl ethers by phosphite compounds containing the bis-cyclic structure of spiro phosphites, both rings being attached to the same tertiary carbon atom in the phosphite molecule.

Abstract: A method of generating a vector set, said vector set being used for testing sequential circuits. The method comprises selecting a plurality of fault models, identifying a fault list each for each of said plurality of fault models, identifying a vector set each for each of said fault lists, selecting a tolerance limit each for each of said fault lists, thereby each fault model having an associated fault list, an associated vector set and an associated tolerance limit, compacting each of said vector set such that the compacted vector set identifies all the faults in the associated fault list or a drop in fault list coverage is within the associated tolerance limit; and creating a vector set by combining all vector sets compacted. A system and a computer program product for testing circuits with a compacted vector set where the compacted vector set is created by dropping faults based on a tolerance limit.

Abstract: A method for automatically mapping state elements between a first circuit and a second circuit is described. The method proceeds by comparing, in a structural phase, structural features of state elements in the first circuit to structural features of state elements in the second circuit for equivalence. Mappings between state elements of the first circuit and the second circuit are determined based on the comparison of structural features. “Don't care” input conditions are then accounted for prior to determination of functional features. During an inversion detection phase, the polarity of the mappings found in the prior structural phase are determined. A functional phase follows in which the functionality of state elements in the first circuit are compared to the functionality of state elements in the second circuit for equivalence using a three-valued random simulation and further mappings are determined based upon the functional comparison.

Abstract: A method of solving a test generation problem for sequential circuits is disclosed. The method comprises recursively dividing an original test generation problem into smaller problems, wherein said sub-problems may be dependent while one or more of said dependent sub-problems may have solution-specific independence, finding solutions for said sub-problems, reusing solutions for dependent sub-problems, whenever the dependent sub-problems enjoy solution-specific independence; and identifying a minimal subset of conflicting objectives if a sub-problem that has to be solved to achieve multiple objectives has no solution. A test generation system comprising a computer, said computer having a cpu and memory, said memory comprising instructions capable of implementing components of said system.

Abstract: Cross-linked toner resin having linear portions and cross-linked portions of high density microgel particles, where the toner resin is an unsaturated polyester resin, is prepared using a liquid chemical initiator such as 1,1-bis(t-butyl peroxy)-3,3,5-trimethylcyclohexane so that the cross-linked resin achieved contains less than 0.20 percent by weight of acids. In particular, the cross-linked toner resin is free of benzoic acid. The method of making the cross-linked toner resin includes (a) spraying the liquid chemical initiator onto the unsaturated polyester resin prior to, during or subsequent to melting of the unsaturated polyester resin to form a polymer melt; and (b) subsequently cross-linking the polymer melt under high shear to form the cross-linked toner resin.

Abstract: A hybrid HardWire device is provided that comprises a gate array core and a set of mask programmable I/O cells having I/O characteristics similar to those of an FPGA, i.e., sufficiently the same so the HardWire device can be used as a drop-in replacement for the FPGA with no redesign of the original system. Using this HardWire device, a user's design originally implemented in an FPGA can be emulated in the HardWire device, which then replaces the FPGA in the same board at a lower cost. In another embodiment, the I/O cells are mask programmable such that they can emulate the I/O characteristics of FPGAs from any of two or more FPGA families. This ability reduces the number of separate HardWire devices that must be designed, manufactured, tested, stored, and sold, and also simplifies the software required to convert designs to the new device. Some embodiments of the invention can also emulate other programmable devices such as PLDs.

Abstract: A mask programmable IC is provided that includes dedicated boundary scan logic in the I/O cells. Valuable core logic resources therefore need not be consumed to implement boundary scan logic. In one embodiment, one boundary scan cell is provided per I/O cell. Another embodiment provides great flexibility in emulating any of several FPGAs in any of several packages. In this embodiment, two boundary scan cells are provided for each I/O pad, each cell alone being capable of providing the boundary scan functions associated with one I/O pad. By selectively choosing which of the boundary scan cells are included in the boundary scan data chain, the order of the boundary scan chain of the emulated FPGA in any of two or more packages can be reproduced. Boundary scan behavior is therefore emulated as well as the programmable logic behavior of the FPGA. In one embodiment, additional programmable interconnect lines traversing each boundary scan cell are provided.

Abstract: A two phase vector restoration technique which extracts a minimal subsequence from a sequence that detects a chosen set of faults is provided. The disclosed vector restoration technique is useful in static compaction of test sequences and in fault diagnosis. An accelerated two phase vector restoration that provides further improvement is also provided. The present invention is a significant improvement over the state of the art in the following ways: (1) a sequence of length n can be restored with only O(n log2n) simulations while known approaches require simulation of O(n2) vectors, (2) a two-step restoration process is used that makes vector restoration practical for large designs, and (3) restoration process for several faults is overlapped to provide significant acceleration in vector restoration. The described vector restoration technique has been integrated into a static test sequence compaction system.

Abstract: The present invention relates to a process for coating a substrate which comprises (a) contacting said substrate with a low volatility organic (so-called "low VOC") coating composition having a viscosity as measured by ZAHN cup 2 of less than about 200 seconds and consisting essentially of at least one polyisocyanate, a solvent in an amount of between 0% and 45% by weight based upon the amount of said polyisocyanate in said composition, and an trimerization catalyst, said composition being essentially free of any volatile mono- and di-isocyanates, to form a coating on said substrate, and (b) heating said coating to a curing temperature of between 120.degree. F. and 350.degree. F. for a curing time of between about ten minutes and about six hours in order to cure said coating by trimerizing at least some of the isocyanate groups of the polyisocyanate to provide a heat-cured coating on said substrate. Also claimed is the coating composition itself.

Abstract: A method of implementing a boundary scan chain is provided using a programmable IC that includes dedicated boundary scan logic having a programmable boundary scan bit-order. Boundary scan cells are provided, each cell being capable of providing the boundary scan functions associated with one I/O pad. In a mask programmable device, dedicated tracks are provided for adding mask programmable interconnect lines. In other programmable ICs such as FPGAs or PLDs, programmable interconnect lines are provided. In either case, the interconnect lines are used to implement the boundary scan data chain. Using these lines, the programmed device can "swap the order" of I/O cells in the boundary scan data chain, or leave cells out of the chain entirely. In one embodiment, the interconnect lines traverse each cell, programmably connecting the data inputs and outputs of adjacent or non-adjacent boundary scan cells.

Abstract: A hybrid HardWire device is provided that comprises a gate array core and a set of mask programmable I/O cells having I/O characteristics similar to those of an FPGA, i.e., sufficiently the same so the HardWire device can be used as a drop-in replacement for the FPGA with no redesign of the original system. Using this HardWire device, a user's design originally implemented in an FPGA can be emulated in the HardWire device, which then replaces the FPGA in the same board at a lower cost. In another embodiment, the I/O cells are mask programmable such that they can emulate the I/O characteristics of FPGAs from any of two or more FPGA families. This ability reduces the number of separate HardWire devices that must be designed, manufactured, tested, stored, and sold, and also simplifies the software required to convert designs to the new device. Some embodiments of the invention can also emulate other programmable devices such as PLDs.