Patents by Inventor Kiran Bondalapati

Kiran Bondalapati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120159224
    Abstract: A processor is configured to support a plurality of performance states and idle states. The processor includes a first programmable location associated with a first idle state and configured to store first entry performance state (P-State) information. The first entry P-State information identifies a first entry P-State. The processor is configured to receive a request to enter the first idle state, retrieve the first entry P-State information and enter the first entry P-State. The processor may include a second programmable location associated with the first idle state and configured to store first exit P-State information. The first exit P-State information identifies a first exit P-State. The processor may be configured to receive a request to exit the first idle state, retrieve the first exit P-State information and enter the first exit P-State.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 21, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Kiran Bondalapati, Magiting M. Talisayon
  • Publication number: 20120144215
    Abstract: The maximum current is limited in a multi-processor core system by monitoring the latest power consumption in the processor cores, in order to prevent a system shutdown as a result of an over-current event. If the sum of the latest power of the processor cores exceeds a threshold limit, a performance state (P-state) limit is enforced in the processor cores. The P-state limit causes a P-state change to a lower frequency, voltage and thus a lower current.
    Type: Application
    Filed: December 3, 2010
    Publication date: June 7, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Samuel D. Naffziger, John P. Petry, Kiran Bondalapati
  • Publication number: 20120144221
    Abstract: A method and apparatus for load step, or instantaneous current spike, mitigation are provided. In the method and apparatus, load steps are mitigated if a computer system a whole is lightly load, which may be determined by the power consumption of the computer system. Further, load steps are mitigated if a number of processor cores capable of inducing a load step is higher than a threshold. The Advanced Configuration and Power Interface (ACPI) performance state of the cores is used to determine a core's potential for generating a load step. A processor core is instructed to mitigate load steps if conditions are met for the mitigation.
    Type: Application
    Filed: December 2, 2010
    Publication date: June 7, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Samuel D. Naffziger, John P. Petry, Kiran Bondalapati
  • Publication number: 20110296412
    Abstract: Approaches for executing untrusted software on a client without compromising the client using micro-virtualization to execute untrusted software in isolated contexts. A template for instantiating a virtual machine on a client is identified in response to receiving a request to execute an application. After the template is identified, without human intervention, a virtual machine is instantiated, using the template, in which the application is to be executed. The template may be selected from a plurality of templates based on the nature of the request, as each template describe characteristics of a virtual machine suitable for a different type of activity. Selected resources such as files are displayed to the virtual machines according to user and organization policies and controls. When the client determines that the application has ceased to execute, the client ceases execution of the virtual machine without human intervention.
    Type: Application
    Filed: May 25, 2011
    Publication date: December 1, 2011
    Inventors: Gaurav Banga, Ian Pratt, Kiran Bondalapati, Vikram Kapoor
  • Publication number: 20110289332
    Abstract: Techniques for power management in a multi-processor system are disclosed. One of the processors in the system monitors whether all threads on all central processing unit (CPU) cores in the multi-processor system halt, and send a message to a south bridge to cause at least a part of the system to enter a low power state if all threads in the multi-processor system halt. The processor sends another message to the south bridge to cause at least a part of the multi-processor system to wake up if at least one thread on any CPU core in the multi-processor system exits a halt.
    Type: Application
    Filed: May 24, 2010
    Publication date: November 24, 2011
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Kiran Bondalapati, William Alexander Hughes, Ming So, Xiaogang Zheng