Patents by Inventor Kiran Buch

Kiran Buch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Massage apparatus, system and method capable of deriving a parameter of an individual
    Patent number: 12097330
    Abstract: Disclosed is a massage apparatus including a processor configurable to receive a first dataset associated with a physiological parameter of an individual to derive a first emotional indication of the individual; wherein the first emotional indication and the first dataset are configured as inputs to derive a second emotional indication of the individual.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: September 24, 2024
    Assignee: OSIM INTERNATIONAL PTE. LTD.
    Inventors: Kia Tong Tan, Gilbert Realuyo, Rui Zou, Kiran Buch
  • MASSAGE APPARATUS, SYSTEM AND METHOD CAPABLE OF DERIVING A PARAMETER OF AN INDIVIDUAL
    Publication number: 20210308415
    Abstract: Disclosed is a massage apparatus including a processor configurable to receive a first dataset associated with a physio-logical parameter of an individual to derive a first emotional indication of the individual; wherein the first emotional indication and the first dataset are configured as inputs to derive a second emotional indication of the individual.
    Type: Application
    Filed: December 26, 2018
    Publication date: October 7, 2021
    Applicant: OSIM INTERNATIONAL PTE. LTD.
    Inventors: Kia Tong TAN, Gilbert REALUYO, Rui ZOU, Kiran BUCH
  • Method for verifying timing in a hard-wired IC device modeled from an FPGA
    Patent number: 6625788
    Abstract: A method and system for converting an architecture-specific design of a first type into an architecture-specific design of a second type such that race conditions and other anomalies are detected in the second type. By identifying routing delays in a first architecture and what those same routing delays would be in a second architecture, the method and system verify that a design has been properly converted. The method and system are applicable to the conversion of programmable interconnect logic devices to mask programmable logic devices. For example, a method for verifying timing for a design implemented in a new device when the design is to be moved from an old device. The method is particularly useful for verifying timing in a mask programmable device (HardWire) when the design is being converted from a field programmable device (FPGA).
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: September 23, 2003
    Assignee: Xilinx, Inc.
    Inventors: Mehul Vashi, Kiran Buch
  • Method for verifying timing in a hard-wired IC device modeled from an FPGA
    Patent number: 6219819
    Abstract: A method and system for converting an architecture-specific design of a first type into an architecture-specific design of a second type such that race conditions and other anomalies are detected in the second type. By identifying routing delays in a first architecture and what those same routing delays would be in a second architecture, the method and system verify that a design has been properly converted. The method and system are applicable to the conversion of programmable interconnect logic devices to mask programmable logic devices. For example, a method for verifying timing for a design implemented in a new device when the design is to be moved from an old device. The method is particularly useful for verifying timing in a mask programmable device (HardWire) when the design is being converted from a field programmable device (FPGA).
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: April 17, 2001
    Assignee: Xilinx, Inc.
    Inventors: Mehul Vashi, Kiran Buch