Abstract: Methods and apparatus relating to techniques for. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to determine a first line and a second line which define a chord to approximate a curve in two-dimensional (2D) space; and extend first line and the second line to a three-dimensional (3D) space using a line approximation between the 2D space and the 3D space. Other embodiments are also disclosed and claimed.

Abstract: A mechanism is described to facilitate microcontroller-based flexible thread scheduling launching in computing environments. An apparatus of embodiments, as described herein, includes facilitating a graphics processor hosting a microcontroller having a thread scheduling unit, and detection and observation logic to detect a scheduling algorithm associated with an application at the apparatus. The apparatus may further include reading and dispatching logic to facilitate the microcontroller to prepare a flexible dispatch routine based on the scheduling algorithm. The apparatus may further include scheduling and launching logic to facilitate the thread scheduling unit to dynamically schedule and launch threads based on the flexible dispatch routine, where the threads are hosted by the graphics processor.

Abstract: Methods and apparatus relating to techniques for dynamic control of liquid cooling pumps to provide thermal cooling uniformity are described. In an embodiment, modification is made to operation of one or more of: one or more cooling pumps or one or more fans, based at least in part on comparison of one or more detected temperature or noise values at one or more components of a processor with one or more corresponding threshold values. The processor may include the logic that causes the modification and one or more sensors. The sensors are thermally or acoustically coupled to the one or more components of the processor to determine the detected temperature or noise values. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive a completion acknowledgment from the plurality of graphics processing units and in response to a determination that the workload is finished, to terminate one or more communication connections on the interconnect bridge. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive, in a read/modify/write (RMW) pipeline, a cache access request from a requestor, wherein the cache request comprises a cache set identifier associated with requested data in the cache set, determine whether the cache set associated with the cache set identifier is in an inaccessible invalid state, and in response to a determination that the cache set is in an inaccessible state or an invalid state, to terminate the cache access request. Other embodiments are also disclosed and claimed.

Abstract: One embodiment provides for a graphics processor comprising a translation lookaside buffer (TLB) to cache a first page table entry for a virtual to physical address mapping for use by the graphics processor, the first page table entry to indicate that a first virtual page is cleared to a clear color and a graphics pipeline to bypass a memory access for the first virtual page based on the first page table entry, wherein the graphics pipeline is to read a field in the first page table entry to determine a value of the clear color.

Abstract: A mechanism is described to facilitate microcontroller-based flexible thread scheduling launching in computing environments. An apparatus of embodiments, as described herein, includes facilitating a graphics processor hosting a microcontroller having a thread scheduling unit, and detection and observation logic to detect a scheduling algorithm associated with an application at the apparatus. The apparatus may further include reading and dispatching logic to facilitate the microcontroller to prepare a flexible dispatch routine based on the scheduling algorithm. The apparatus may further include scheduling and launching logic to facilitate the thread scheduling unit to dynamically schedule and launch threads based on the flexible dispatch routine, where the threads are hosted by the graphics processor.

Abstract: In accordance with one embodiment each page table entry maps a variable page size (per entry), if multiple continuous virtual pages map to contiguous physical pages. This may drastically reduce the number of translation lookaside buffer (TLB) entries needed since each entry can potentially map a larger chunk of memory, in some embodiments.

Abstract: Methods and apparatus relating to techniques for dynamic control of liquid cooling pumps to provide thermal cooling uniformity are described. In an embodiment, modification is made to operation of one or more of: one or more cooling pumps or one or more fans, based at least in part on comparison of one or more detected temperature or noise values at one or more components of a processor with one or more corresponding threshold values. The processor may include the logic that causes the modification and one or more sensors, The sensors are thermally or acoustically coupled to the one or more components of the processor to determine the detected temperature or noise values. Other embodiments are also disclosed and claimed.

Abstract: One embodiment provides for a graphics processor comprising a translation lookaside buffer (TLB) to cache a first page table entry for a virtual to physical address mapping for use by the graphics processor, the first page table entry to indicate that a first virtual page is cleared to a clear color and a graphics pipeline module to bypass a memory access for the first virtual page based on the first page table entry.

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive metadata from an application, wherein the meta data indicates one or more processing operations which can accommodate a predetermined level of bit errors in read operations from memory, determine, from the metadata, pixel data for which error correction code bypass is acceptable, and generate one or more error correction code bypass hints for subsequent cache access to the pixel data for which error correction code bypass is acceptable, and transmit the one or more error correction code bypass hints to a graphics processing pipeline. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive a completion acknowledgment from the plurality of graphics processing units and in response to a determination that the workload is finished, to terminate one or more communication connections on the interconnect bridge. Other embodiments are also disclosed and claimed.

Abstract: Embodiments are generally directed to area-efficient implementations of graphics instructions. An embodiment of an apparatus includes one or more processors to process data, including generating multiple sets of data including at least a first data set and a second data set for a data application; a memory for the storage of data; and a delta compression engine, the delta compression engine being operable to perform a selected delta compression operation on the generated plurality of sets of data. The delta compression operation includes multiple orders of delta compression to be performed on the second data set based on differences with the first data set, the orders of delta compression including a first order delta and a second order delta. Each of the orders of delta compression includes one of multiple data encoding processes, the data encoding processing including a first data encoding process and a second, different data encoding process.

Abstract: An apparatus and method for pre-decompression filtering of compressed texel data.

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive, in a read/modify/write (RMW) pipeline, a cache access request from a requestor, wherein the cache request comprises a cache set identifier associated with requested data in the cache set, determine whether the cache set associated with the cache set identifier is in an inaccessible invalid state, and in response to a determination that the cache set is in an inaccessible state or an invalid state, to terminate the cache access request. Other embodiments are also disclosed and claimed.

Abstract: In accordance with one embodiment each page table entry maps a variable page size (per entry), if multiple continuous virtual pages map to contiguous physical pages. This may drastically reduce the number of translation lookaside buffer (TLB) entries needed since each entry can potentially map a larger chunk of memory, in some embodiments.

Abstract: In accordance with one embodiment each page table entry maps a variable page size (per entry), if multiple continuous virtual pages map to contiguous physical pages. This may drastically reduce the number of translation lookaside buffer (TLB) entries needed since each entry can potentially map a larger chunk of memory, in some embodiments.

Abstract: Methods and apparatus relating to techniques for dynamic control of liquid cooling pumps to provide thermal cooling uniformity are described. In an embodiment, modification is made to operation of one or more of: one or more cooling pumps or one or more fans, based at least in part on comparison of one or more detected temperature or noise values at one or more components of a processor with one or more corresponding threshold values. The processor may include the logic that causes the modification and one or more sensors, The sensors are thermally or acoustically coupled to the one or more components of the processor to determine the detected temperature or noise values. Other embodiments are also disclosed and claimed.

Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to assemble a general register file (GRF) message and hold the GRF message in storage in a data port until all data for the GRF message is received. Other embodiments are also disclosed and claimed.

Abstract: One embodiment provides for a graphics processor comprising a translation lookaside buffer (TLB) to cache a first page table entry for a virtual to physical address mapping for use by the graphics processor, the first page table entry to indicate that a first virtual page is cleared to a clear color and a graphics pipeline module to bypass a memory access for the first virtual page based on the first page table entry.