Patents by Inventor Kiran Chatty

Kiran Chatty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9853147
    Abstract: A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: December 26, 2017
    Assignee: Monolith Semiconductor Inc.
    Inventors: Sujit Banerjee, Kevin Matocha, Kiran Chatty
  • Publication number: 20170178989
    Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.
    Type: Application
    Filed: March 1, 2017
    Publication date: June 22, 2017
    Inventors: Kevin MATOCHA, John NOWAK, Kiran CHATTY, Sujit BANERJEE
  • Publication number: 20170133503
    Abstract: A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias. The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.
    Type: Application
    Filed: January 23, 2017
    Publication date: May 11, 2017
    Inventors: Kevin MATOCHA, Kiran CHATTY, Sujit BANERJEE
  • Patent number: 9620428
    Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: April 11, 2017
    Assignee: MONOLITH SEMICONDUCTOR INC.
    Inventors: Kevin Matocha, John Nowak, Kiran Chatty, Sujit Banerjee
  • Patent number: 9583482
    Abstract: A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias. The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: February 28, 2017
    Assignee: MONOLITH SEMICONDUCTOR INC.
    Inventors: Kevin Matocha, Kiran Chatty, Sujit Banerjee
  • Publication number: 20160343631
    Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.
    Type: Application
    Filed: July 22, 2016
    Publication date: November 24, 2016
    Inventors: Kevin MATOCHA, John NOWAK, Kiran CHATTY, Sujit BANERJEE
  • Patent number: 9425153
    Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: August 23, 2016
    Assignee: MONOLITH SEMICONDUCTOR INC.
    Inventors: Kevin Matocha, John Nowak, Kiran Chatty, Sujit Banerjee
  • Publication number: 20160233210
    Abstract: A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias. The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.
    Type: Application
    Filed: February 11, 2015
    Publication date: August 11, 2016
    Inventors: Kevin MATOCHA, Kiran CHATTY, Sujit BANERJEE
  • Publication number: 20160104792
    Abstract: A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.
    Type: Application
    Filed: December 11, 2015
    Publication date: April 14, 2016
    Inventors: Sujit BANERJEE, Kevin MATOCHA, Kiran CHATTY
  • Publication number: 20160093733
    Abstract: A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.
    Type: Application
    Filed: December 9, 2015
    Publication date: March 31, 2016
    Inventors: Sujit BANERJEE, Kevin MATOCHA, Kiran CHATTY
  • Patent number: 9214572
    Abstract: A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: December 15, 2015
    Assignee: MONOLITH SEMICONDUCTOR INC.
    Inventors: Sujit Banerjee, Kevin Matocha, Kiran Chatty
  • Publication number: 20150214164
    Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.
    Type: Application
    Filed: April 7, 2015
    Publication date: July 30, 2015
    Inventors: Kevin MATOCHA, John NOWAK, Kiran CHATTY, Sujit BANERJEE
  • Patent number: 9035395
    Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: May 19, 2015
    Assignee: MONOLITH SEMICONDUCTOR, INC.
    Inventors: Kevin Matocha, Kiran Chatty, Larry Rowland, Kalidas Chatty
  • Patent number: 8994118
    Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: March 31, 2015
    Assignee: Monolith Semiconductor, Inc.
    Inventors: Kevin Matocha, Kiran Chatty, Larry Rowland, Kalidas Chatty
  • Publication number: 20150084066
    Abstract: A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.
    Type: Application
    Filed: August 11, 2014
    Publication date: March 26, 2015
    Inventors: Sujit BANERJEE, Kevin MATOCHA, Kiran CHATTY
  • Publication number: 20140367771
    Abstract: Metal-oxide-semiconductor field-effect transistor (MOSFET) devices are described which have a p-type region between the p-type well regions of the device. The p-type region can be either floating or connected to the p-type well regions by additional p-type regions. MOSFET devices are also described which have one or more p-type regions connecting the p-type well regions of the device. The p-type well regions can be arranged in a various geometric arrangements including square, diamond and hexagonal. Methods of making the devices are also described.
    Type: Application
    Filed: June 12, 2014
    Publication date: December 18, 2014
    Inventors: Kiran CHATTY, Kevin MATOCHA, Sujit BANERJEE, Larry Burton ROWLAND
  • Patent number: 8884270
    Abstract: Vertical junction field effect transistors (VJFETs) having improved heat dissipation at high current flow while maintaining the desirable specific on-resistance and normalized saturated drain current properties characteristic of devices having small pitch lengths are described. The VJFETs comprise one or more electrically active source regions in electrical contact with the source metal of the device and one or more electrically inactive source regions not in electrical contact with the source metal of the device. The electrically inactive source regions dissipate heat generated by the electrically active source regions during current flow.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: November 11, 2014
    Assignee: Power Integrations, Inc.
    Inventors: Janna Casady, Jeffrey Casady, Kiran Chatty, David Sheridan, Andrew Ritenour
  • Publication number: 20140299890
    Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described.
    Type: Application
    Filed: May 1, 2014
    Publication date: October 9, 2014
    Applicant: Monolith Semiconductor, Inc.
    Inventors: Kevin Matocha, Kiran Chatty, Larry Rowland, Kalidas Chatty
  • Publication number: 20140299887
    Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described.
    Type: Application
    Filed: April 4, 2014
    Publication date: October 9, 2014
    Applicant: Monolith Semiconductor, Inc.
    Inventors: Kevin Matocha, Kiran Chatty, Larry Rowland, Kalidas Chatty
  • Publication number: 20120261675
    Abstract: Vertical junction field effect transistors (VJFETs) having improved heat dissipation at high current flow while maintaining the desirable specific on-resistance and normalized saturated drain current properties characteristic of devices having small pitch lengths are described. The VJFETs comprise one or more electrically active source regions in electrical contact with the source metal of the device and one or more electrically inactive source regions not in electrical contact with the source metal of the device. The electrically inactive source regions dissipate heat generated by the electrically active source regions during current flow.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 18, 2012
    Applicant: SS SC IP, LLC
    Inventors: Janna CASADY, Jeffrey CASADY, Kiran CHATTY, David SHERIDAN, Andrew RITENOUR