Patents by Inventor Kiran Ganesh

Kiran Ganesh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • 2-dimensional placement with reliability constraints for VLSI design
    Patent number: 6823500
    Abstract: A 2-dimensional placement system and method minimize reliability concerns arising from electromigration and self-heat while at the same time achieving a high layout density. The 2-dimensional placement method also uses a placement space with rows that have non-uniform sizes and are overlapping. According to one embodiment of the present invention, a computerized method of creating a layout for a circuit design includes receiving a circuit design and receiving at least one layout rule based on a reliability verification constraint for the circuit design. The computerized method further includes generating a layout for the circuit design through computer automated operations wherein the layout generated satisfies the at least one layout rule based on the reliability verification constraint received for the circuit design.
    Type: Grant
    Filed: November 1, 1999
    Date of Patent: November 23, 2004
    Assignee: Intel Corporation
    Inventors: Kiran Ganesh, Artour Levin, Miles F. McCoo, Naresh K. Sehgal