Abstract: There is described a driver circuit for a single wire protocol slave unit, the driver circuit comprising (a) at least one current mirror comprising a first transistor (MP1, MN3) and a second transistor (MP2, MN4), wherein the gate of both transistors is connected to a bias node (PBIAS, S2BIAS), and wherein the second transistor is adapted to conduct a mirror current (I2, IOUT) equal to a current (I1, I2) conducted by the first transistor multiplied by a predetermined factor, (b) a bias transistor (MP3, MN5) for selectively connecting and disconnecting the bias node to and from a predetermined potential (VDD, GND) in response to a control signal (ABUF, AN), and (c) a current boosting element for providing a boost current (I1P, I2P) to the bias node for a predetermined period of time when the control signal causes the bias transistor to disconnect the bias node from the predetermined potential. There is also described a universal integrated circuit card device comprising a driver circuit.

Abstract: A glitch filter circuit has a filter/delay part that always operates on rising or falling pulses for both rising edges and falling edges of the input signal. In this way, the filter delay can be made symmetrical and the circuit will have no duty cycle distortion. The rise and fall delays will track each other when there are PVT (Process, Voltage and Temperature) variations.

Abstract: There is described a driver circuit for a single wire protocol slave unit, the driver circuit comprising (a) at least one current mirror comprising a first transistor (MP1, MN3) and a second transistor (MP2, MN4), wherein the gate of both transistors is connected to a bias node (PBIAS, S2BIAS), and wherein the second transistor is adapted to conduct a mirror current (I2, IOUT) equal to a current (I1, I2) conducted by the first transistor multiplied by a predetermined factor, (b) a bias transistor (MP3, MN5) for selectively connecting and disconnecting the bias node to and from a predetermined potential (VDD, GND) in response to a control signal (ABUF, AN), and (c) a current boosting element for providing a boost current (I1P, I2P) to the bias node for a predetermined period of time when the control signal causes the bias transistor to disconnect the bias node from the predetermined potential. There is also described a universal integrated circuit card device comprising a driver circuit.

Abstract: A glitch filter circuit has a filter/delay part that always operates on rising or falling pulses for both rising edges and falling edges of the input signal. In this way, the filter delay can be made symmetrical and the circuit will have no duty cycle distortion. The rise and fall delays will track each other when there are PVT (Process, Voltage and Temperature) variations.