Patents by Inventor Kiran K. Gunnam

Kiran K. Gunnam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240036207
    Abstract: Methods and systems for improved simultaneous localization and mapping based on 3-D LIDAR image data are presented herein. In one aspect, LIDAR image frames are segmented and clustered before feature detection to improve computational efficiency while maintaining both mapping and localization accuracy. Segmentation involves removing redundant data before feature extraction. Clustering involves grouping pixels associated with similar objects together before feature extraction. In another aspect, features are extracted from LIDAR image frames based on a measured optical property associated with each measured point. The pools of feature points comprise a low resolution feature map associated with each image frame. Low resolution feature maps are aggregated over time to generate high resolution feature maps.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 1, 2024
    Applicant: Velodyne Lidar USA, Inc.
    Inventor: Kiran K. Gunnam
  • Patent number: 11821987
    Abstract: Methods and systems for improved simultaneous localization and mapping based on 3-D LIDAR image data are presented herein. In one aspect, LIDAR image frames are segmented and clustered before feature detection to improve computational efficiency while maintaining both mapping and localization accuracy. Segmentation involves removing redundant data before feature extraction. Clustering involves grouping pixels associated with similar objects together before feature extraction. In another aspect, features are extracted from LIDAR image frames based on a measured optical property associated with each measured point. The pools of feature points comprise a low resolution feature map associated with each image frame. Low resolution feature maps are aggregated over time to generate high resolution feature maps.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: November 21, 2023
    Assignee: Velodyne Lidar USA, Inc.
    Inventor: Kiran K. Gunnam
  • Publication number: 20230042797
    Abstract: Methods and systems for controlling illumination power of a LIDAR based, three dimensional imaging system based on discrete illumination power tiers are described herein. In one aspect, the illumination intensity of a pulsed beam of illumination light emitted from a LIDAR system is varied in accordance with a set of illumination power tiers based on the difference between a desired and a measured return pulse. In a further aspect, the illumination power tier is selected based on whether an intensity difference exceeds one of a sequence of predetermined, tiered threshold values. In this manner, the intensity of measured return pulses is maintained within a linear range of the analog to digital converter for objects detected over a wide range of distances from the LIDAR system and a wide range of environmental conditions in the optical path between the LIDAR system and the detected object.
    Type: Application
    Filed: August 15, 2022
    Publication date: February 9, 2023
    Inventor: Kiran K. Gunnam
  • Patent number: 11415681
    Abstract: Methods and systems for controlling illumination power of a LIDAR based, three dimensional imaging system based on discrete illumination power tiers are described herein. In one aspect, the illumination intensity of a pulsed beam of illumination light emitted from a LIDAR system is varied in accordance with a set of illumination power tiers based on the difference between a desired and a measured return pulse. In a further aspect, the illumination power tier is selected based on whether an intensity difference exceeds one of a sequence of predetermined, tiered threshold values. In this manner, the intensity of measured return pulses is maintained within a linear range of the analog to digital converter for objects detected over a wide range of distances from the LIDAR system and a wide range of environmental conditions in the optical path between the LIDAR system and the detected object.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: August 16, 2022
    Assignee: VELODYNE LIDAR USA, INC.
    Inventor: Kiran K. Gunnam
  • Publication number: 20200025896
    Abstract: Methods and systems for controlling illumination power of a LIDAR based, three dimensional imaging system based on discrete illumination power tiers are described herein. In one aspect, the illumination intensity of a pulsed beam of illumination light emitted from a LIDAR system is varied in accordance with a set of illumination power tiers based on the difference between a desired and a measured return pulse. In a further aspect, the illumination power tier is selected based on whether an intensity difference exceeds one of a sequence of predetermined, tiered threshold values. In this manner, the intensity of measured return pulses is maintained within a linear range of the analog to digital converter for objects detected over a wide range of distances from the LIDAR system and a wide range of environmental conditions in the optical path between the LIDAR system and the detected object.
    Type: Application
    Filed: January 10, 2019
    Publication date: January 23, 2020
    Inventor: Kiran K. Gunnam
  • Publication number: 20190079193
    Abstract: Methods and systems for improved simultaneous localization and mapping based on 3-D LIDAR image data are presented herein. In one aspect, LIDAR image frames are segmented and clustered before feature detection to improve computational efficiency while maintaining both mapping and localization accuracy. Segmentation involves removing redundant data before feature extraction. Clustering involves grouping pixels associated with similar objects together before feature extraction. In another aspect, features are extracted from LIDAR image frames based on a measured optical property associated with each measured point. The pools of feature points comprise a low resolution feature map associated with each image frame. Low resolution feature maps are aggregated over time to generate high resolution feature maps.
    Type: Application
    Filed: September 13, 2018
    Publication date: March 14, 2019
    Inventor: Kiran K. Gunnam
  • Patent number: 9659637
    Abstract: A storage device may include a processor and a memory device including a multilevel memory cell. The processor may correlate a first physical page address and a second physical page address, each address being associated with the multilevel memory cell. The processor also may apply a first read operation to the memory cell to determine a value of a first bit associated with the first physical page address. The processor additionally may apply at least a second read operation to the multilevel memory cell to determine a value of a second bit associated with the second physical page address. The processor may determine, based at least in part on the value of the first bit and the value of the second bit, a soft decision value associated with the second bit. The processor may verify the value of the second bit based at least in part on the soft decision value.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: May 23, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventors: Seung-Hwan Song, Kiran K. Gunnam, Zvonimir Z. Bandic
  • Publication number: 20170047114
    Abstract: A storage device may include a processor and a memory device including a multilevel memory cell. The processor may correlate a first physical page address and a second physical page address, each address being associated with the multilevel memory cell. The processor also may apply a first read operation to the memory cell to determine a value of a first bit associated with the first physical page address. The processor additionally may apply at least a second read operation to the multilevel memory cell to determine a value of a second bit associated with the second physical page address. The processor may determine, based at least in part on the value of the first bit and the value of the second bit, a soft decision value associated with the second bit. The processor may verify the value of the second bit based at least in part on the soft decision value.
    Type: Application
    Filed: August 11, 2015
    Publication date: February 16, 2017
    Inventors: Seung-Hwan Song, Kiran K. Gunnam, Zvonimir Z. Bandic
  • Patent number: 8418023
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes a control unit that controls decoder processing, the control unit causing the decoder to process the blocks of a low density parity check (“LDPC”) matrix out of order. A decoder embodiment may process the layers of the LDPC matrix out of order and/or perform partial state processing on out of order blocks of the LDPC matrix and/or generate R messages out of order.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: April 9, 2013
    Assignee: The Texas A&M University System
    Inventors: Kiran K. Gunnam, Gwan S. Choi
  • Patent number: 8359522
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: January 22, 2013
    Assignee: Texas A&M University System
    Inventors: Kiran K. Gunnam, Gwan S. Choi
  • Publication number: 20080301521
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes a control unit that controls decoder processing, the control unit causing the decoder to process the blocks of a low density parity check (“LDPC”) matrix out of order. A decoder embodiment may process the layers of the LDPC matrix out of order and/or perform partial state processing on out of order blocks of the LDPC matrix and/or generate R messages out of order.
    Type: Application
    Filed: May 1, 2008
    Publication date: December 4, 2008
    Applicant: TEXAS A&M UNIVERSITY SYSTEM
    Inventors: Kiran K. GUNNAM, Gwan S. CHOI
  • Publication number: 20080276156
    Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.
    Type: Application
    Filed: May 1, 2008
    Publication date: November 6, 2008
    Applicant: TEXAS A&M UNIVERSITY SYSTEM
    Inventors: Kiran K. GUNNAM, Gwan S. CHOI