Abstract: A method facilitates simulating a plurality of circuit elements connected to a multiport interconnect structure having a first set of ports. The method includes: receiving a first set of data that models electrical behavior of the first set of ports and a first portion of the plurality of circuit elements; determining a first subset of the first data, which models electrical behavior of a set of exposed ports of the first set of ports, and a second subset of the first data, which models electrical behavior of a set of non-exposed ports of the first set of ports and the first portion of the plurality of circuit elements; and combining the second subset of the first data into the first subset of the first data to generate a second set of data that models electrical behavior of a second interconnect structure having fewer ports than the multiport interconnect structure.

Abstract: A system and method of accelerating sparse matrix operations in full accuracy simulation of a circuit includes determining repetitive blocks of the circuit, determining a set of values of a current block, determining whether the state of the current block is sufficiently close to the state of a stored block solution when the corresponding values are within a predetermined error range, and performing a reduced computation using the stored block solution to provide a solution for the current block when the states are sufficiently close to each other. The reduced computation includes retrieving previously stored solutions and performing substantially simplified matrix and vector operations while maintaining accuracy of the solution. Reduced precision versions of the values may be used to generate a hash index used to store the block solutions. Stored redundant device information may also be used to simplify device solutions in a similar manner.

Abstract: A method facilitates simulating a plurality of circuit elements connected to a multiport interconnect structure having a first set of ports. The method includes: receiving a first set of data that models electrical behavior of the first set of ports and a first portion of the plurality of circuit elements; determining a first subset of the first data, which models electrical behavior of a set of exposed ports of the first set of ports, and a second subset of the first data, which models electrical behavior of a set of non-exposed ports of the first set of ports and the first portion of the plurality of circuit elements; and combining the second subset of the first data into the first subset of the first data to generate a second set of data that models electrical behavior of a second interconnect structure having fewer ports than the multiport interconnect structure.

Abstract: A mechanism for improving speed of simulation of complex circuits that include transistors and other devices that share similar properties is provided. Circuit simulation speed is improved by efficiently identifying transistors and other devices having identical properties that share a same state at the time of interest in the simulation. Transistors and other devices are collected into groups having the same characteristics and topologies prior to simulation. Then during simulation, a determination is made as to whether a previously-evaluated transistor or device in the same group as a presently-being evaluated transistor or device has terminal input values that are the same, or nearly the same. If so, then output values of the previously-evaluated transistor or device are used in calculating the output values of the present transistor or device.

Abstract: A system and method of accelerating sparse matrix operations in full accuracy simulation of a circuit includes determining repetitive blocks of the circuit, determining a set of values of a current block, determining whether the state of the current block is sufficiently close to the state of a stored block solution when the corresponding values are within a predetermined error range, and performing a reduced computation using the stored block solution to provide a solution for the current block when the states are sufficiently close to each other. The reduced computation includes retrieving previously stored solutions and performing substantially simplified matrix and vector operations while maintaining accuracy of the solution. Reduced precision versions of the values may be used to generate a hash index used to store the block solutions. Stored redundant device information may also be used to simplify device solutions in a similar manner.

Abstract: A mechanism for improving speed of simulation of complex circuits that include transistors and other devices that share similar properties is provided. Circuit simulation speed is improved by efficiently identifying transistors and other devices having identical properties that share a same state at the time of interest in the simulation. Transistors and other devices are collected into groups having the same characteristics and topologies prior to simulation. Then during simulation, a determination is made as to whether a previously-evaluated transistor or device in the same group as a presently-being evaluated transistor or device has terminal input values that are the same, or nearly the same. If so, then output values of the previously-evaluated transistor or device are used in calculating the output values of the present transistor or device.

Abstract: A method and apparatus for simulating the design of an integrated circuit uses a processor (200). The processor (200) executes a simulator (540) from memory (280) to exercise a model (544). The data points (15-27) of an output signal are stored in a history data file (542). The techniques used to generate each of the data points (15-27) are also stored in the history data in file (542). The history data are then used to generate a converted output signal that has a uniform time scale. If the converted output signal requires the generation of a desired data point, then the approximation technique used to generate the following data point stored in the history data (542) is used.

Abstract: The present invention generates a model of a graded channel transistor having at least two channel portions of differing doping concentrations. The present invention assumes a uniform doping concentration of each channel portion. Each of the channel portions is modeled using a standard transistor model (100, 120) with junction voltages (64) resulting between the transistor models. The junction voltages (64) are determined to be at a level such that the channel currents of the transistor models (60, 62) are equal. Once the junction voltages (64) are determined, the parameters of the transistor models (60, 62) are determined. Once the transistor models (60, 62) are determined, the models are combined to produce a composite transistor model (70) for the transistor using standard circuit reduction techniques. The composite model produced is scalable with respect to geometry, is continuous, and is differentiable.