Abstract: For high voltage applications, multi-channel successive approximation register (SAR) analog-to-digital converters (ADCs) are often plagued with numerous problems that are generally associated with parasitics (which are present in high voltage components). Here, a different architecture is provided where the sampling capacitors are separated from conversion capacitors so as to have low voltage components in the conversion path. Additionally, to improve the acquisition time and reduced total harmonic distortion (THD) multiple channels can use the same sampling capacitors.

Abstract: For high voltage applications, multi-channel successive approximation register (SAR) analog-to-digital converters (ADCs) are often plagued with numerous problems that are generally associated with parasitics (which are present in high voltage components). Here, a different architecture is provided where the sampling capacitors are separated from conversion capacitors so as to have low voltage components in the conversion path. Additionally, to improve the acquisition time and reduced total harmonic distortion (THD) multiple channels can use the same sampling capacitors.

Abstract: An SAR ADC is operated by sampling an input voltage and redistributing a corresponding charge among the coupling capacitor and a plurality of binarily weighted capacitors of a CDAC array to produce a first voltage on a charge summing conductor. A successive approximation bit testing/conversion operation is performed at a first speed on a first group of bits, beginning with the MSB, to determine the bits of the first group with at least a first level of accuracy. A first error correction operation includes performing a bit testing/conversion operation on a last bit of the first group at a second speed which is lower than the first speed to determine the bits of the first group at least a second level of accuracy which is more accurate than the first level of accuracy. Both the voltage on the charge summing conductor and the bits of the group are incremented or decremented as necessary to elevate the level of accuracy of bits of the first group to at least the second level of accuracy.

Abstract: An SAR ADC is operated by sampling an input voltage and redistributing a corresponding charge among the coupling capacitor and a plurality of binarily weighted capacitors of a CDAC array to produce a first voltage on a charge summing conductor. A successive approximation bit testing/conversion operation is performed at a first speed on a first group of bits, beginning with the MSB, to determine the bits of the first group with at least a first level of accuracy. A first error correction operation includes performing a bit testing/conversion operation on a last bit of the first group at a second speed which is lower than the first speed to determine the bits of the first group at least a second level of accuracy which is more accurate than the first level of accuracy. Both the voltage on the charge summing conductor and the bits of the group are incremented or decremented as necessary to elevate the level of accuracy of bits of the first group to at least the second level of accuracy.