Patents by Inventor Kiran V. Chatty
Kiran V. Chatty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8354722Abstract: An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad.Type: GrantFiled: May 31, 2011Date of Patent: January 15, 2013Assignee: International Business Machines CorporationInventors: John B. Campi, Jr., Shunhua Chang, Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra, Mujahid Muhammad
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Publication number: 20130009207Abstract: A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.Type: ApplicationFiled: September 13, 2012Publication date: January 10, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John B. Campi, JR., Shunhua T. Chang, Kiran V. Chatty, Robert J. Gauthier, JR., Junjun Li, Rahul Mishra, Mujahid Muhammad
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Patent number: 8350329Abstract: An electrostatic discharge (ESD) protection device for an integrated circuit includes a buried layer of a first polarity type formed in a substrate of a second polarity type. A well region of the second polarity type is formed above the buried layer. An FET of the first polarity type is formed within the well region. An inner pair of shallow wells of the first polarity type is disposed adjacent to source and drain diffusion regions of the FET, the inner pair of shallow wells having a depth such that a bottom of the inner pair of shallow wells is above a top of the buried layer. An outer pair of deep wells of the first polarity type extends down to the top of the buried layer such that the outer pair of deep wells and the buried layer define a perimeter of the well region of the second polarity type.Type: GrantFiled: October 19, 2010Date of Patent: January 8, 2013Assignee: International Business Machines CorporationInventors: John B. Campi, Jr., Shunhua T. Chang, Kiran V. Chatty, Robert J Gauthier, Jr., Junjun Li, Rahul Mishra, Mujahid Muhammad
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Patent number: 8349697Abstract: A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.Type: GrantFiled: June 29, 2012Date of Patent: January 8, 2013Assignee: International Business Machines CorporationInventors: Wagdi W. Abadeer, Kiran V. Chatty, Robert J. Gauthier, Jr., Jed H. Rankin, William R. Tonti, Yun Shi
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Publication number: 20120305984Abstract: An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad.Type: ApplicationFiled: May 31, 2011Publication date: December 6, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John B. Campi, JR., Shunhua T. Chang, Kiran V. Chatty, Robert J. Gauthier, JR., Junjun Li, Rahul Mishra, Mujahid Muhammad
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Publication number: 20120280356Abstract: A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region.Type: ApplicationFiled: July 19, 2012Publication date: November 8, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wagdi W. Abadeer, Lilian Kamal, Kiran V. Chatty, Robert J. Gauthier, JR., Jed H. Rankin, Robert R. Robison, William Tonti
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Patent number: 8299533Abstract: A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.Type: GrantFiled: November 24, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: John B. Campi, Jr., Shunhua Chang, Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra, Mujahid Muhammad
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Publication number: 20120264275Abstract: A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.Type: ApplicationFiled: June 29, 2012Publication date: October 18, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wagdi W. Abadeer, Kiran V. Chatty, Robert J. Gauthier, JR., Jed H. Rankin, William R. Tonti, Yun Shi
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Publication number: 20120250195Abstract: An ESD power clamp circuit and method of ESD protection. The ESD power clamp circuit includes: a power clamp device coupled to a resistive/capacitive (RC) network, the RC network including a capacitor as the capacitive element of the RC network and one or more junction field effect transistors (JFETs) configured as variable resistors as the resistive element of the RC network.Type: ApplicationFiled: March 31, 2011Publication date: October 4, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shunhua T. Chang, Kiran V. Chatty, Robert J. Gauthier, JR., Junjun Li, Rahul Mishra, Mujahid Muhammad
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Patent number: 8232177Abstract: A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region.Type: GrantFiled: September 30, 2009Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Wagdi Abadeer, Lilian Kamal, legal representative, Kiran V Chatty, Robert J Gauthier, Jr., Jed H Rankin, Robert R Robison, William Tonti
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Publication number: 20120178222Abstract: Silicon controlled rectifiers (SCR), methods of manufacture and design structures are disclosed herein. The method includes forming a common P-well on a buried insulator layer of a silicon on insulator (SOI) wafer. The method further includes forming a plurality of silicon controlled rectifiers (SCR) in the P-well such that N+ diffusion cathodes of each of the plurality of SCRs are coupled together by the common P-well.Type: ApplicationFiled: January 6, 2011Publication date: July 12, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michel J. ABOU-KHALIL, Kiran V. Chatty, Robert J. Gauthier, JR., Junjun Li
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Patent number: 8216909Abstract: A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.Type: GrantFiled: August 26, 2009Date of Patent: July 10, 2012Assignee: International Business Machines CorporationInventors: Wagdi W. Abadeer, Kiran V. Chatty, Robert J. Gauthier, Jr., Jed H. Rankin, William R. Tonti, Yun Shi
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Publication number: 20120126285Abstract: A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.Type: ApplicationFiled: November 24, 2010Publication date: May 24, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John B. Campi, JR., Shunhua T. Chang, Kiran V. Chatty, Robert J. Gauthier, JR., Junjun Li, Rahul Mishra, Mujahid Muhammad
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Publication number: 20120120531Abstract: A circuit and method for electrostatic discharge (ESD) protection. The ESD protection circuit includes: a silicon control rectifier (SCR) connected between a first voltage rail and a second voltage rail; one or more diodes connected in series in a forward conduction direction between the first voltage rail and a source of a p-channel field effect transistor (PFET); a drain of the PFET connected to the SCR and connected to ground through a current trigger device; and a control circuit connected to the gate of the PFET.Type: ApplicationFiled: November 11, 2010Publication date: May 17, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michel J. Abou-Khalil, Kiran V. Chatty, Robert J. Gauthier, JR.
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Patent number: 8169760Abstract: An integrated circuit, design structures and methods of forming the integrated circuit which includes a signal pad ESD coupled to an I/O signal pad and a power supply ESD coupled to a source VDD. The signal pad ESD and the power supply ESD are integrated in a single ESD structure.Type: GrantFiled: January 19, 2009Date of Patent: May 1, 2012Assignee: International Business Machines CorporationInventors: Shunhua T. Chang, Kiran V. Chatty, Robert J. Gauthier, Jr., Mujahid Muhammad
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Publication number: 20120098087Abstract: Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.Type: ApplicationFiled: January 3, 2012Publication date: April 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wagdi W. Abadeer, Lilian Kamal, Kiran V. Chatty, Jason E. Cummings, Toshiharu Furukawa, Robert J. Gauthier, JR., Jed H. Rankin, Robert R. Robison, William R. Tonti
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Publication number: 20120091530Abstract: An electrostatic discharge (ESD) protection device for an integrated circuit includes a buried layer of a first polarity type formed in a substrate of a second polarity type. A well region of the second polarity type is formed above the buried layer. An FET of the first polarity type is formed within the well region. An inner pair of shallow wells of the first polarity type is disposed adjacent to source and drain diffusion regions of the FET, the inner pair of shallow wells having a depth such that a bottom of the inner pair of shallow wells is above a top of the buried layer. An outer pair of deep wells of the first polarity type extends down to the top of the buried layer such that the outer pair of deep wells and the buried layer define a perimeter of the well region of the second polarity type.Type: ApplicationFiled: October 19, 2010Publication date: April 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John B. Campi, JR., Shunhua T. Chang, Kiran V. Chatty, Robert J. Gauthier, JR., Junjun Li, Rahul Mishra, Mujahid Muhammad
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Publication number: 20120043583Abstract: A low leakage, low capacitance diode based triggered electrostatic discharge (ESD) silicon controlled rectifiers (SCR), methods of manufacture and design structure are provided. The method includes providing a silicon film on an insulator layer. The method further includes forming isolation regions which extend from an upper side of the silicon layer to the insulator layer. The method further includes forming one or more diodes in the silicon layer, including a p+ region and an n+ region formed in a well bordered by the isolation regions. The isolation regions isolate the one or more diodes in a vertical direction and the insulator layer isolates the one or more diodes from an underlying P or N type substrate, in a horizontal direction.Type: ApplicationFiled: August 20, 2010Publication date: February 23, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michel J. ABOU-KHALIL, Shunhua T. CHANG, Kiran V. CHATTY, Robert J. GAUTHIER, JR., Junjun LI, Mujahid MUHAMMAD
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Patent number: 8110483Abstract: Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.Type: GrantFiled: October 22, 2009Date of Patent: February 7, 2012Assignee: International Business Machines CorporationInventors: Wagdi W. Abadeer, Lilian Kamal, legal representative, Kiran V. Chatty, Jason E. Cummings, Toshiharu Furukawa, Robert J. Gauthier, Jed H. Rankin, Jr., Robert R. Robison, William R. Tonti
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Patent number: 8084822Abstract: Fin-FETS and methods of fabricating fin-FETs. The methods include: providing substrate comprising a silicon oxide layer on a top surface of a semiconductor substrate, a stiffening layer on a top surface of the silicon oxide layer, and a single crystal silicon layer on a top surface of the stiffening layer; forming a fin from the single crystal silicon layer; forming a source and a drain in the fin and on opposite sides of a channel region of the fin; forming a gate dielectric layer on at least one surface of the fin in the channel region; and forming a gate electrode on the gate dielectric layer.Type: GrantFiled: September 30, 2009Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: Kiran V. Chatty, Robert J. Gauthier, Jr., Jed Hickory Rankin, Robert R. Robison, William Robert Tonti