Abstract: Systems, methods, and other embodiments associated with mitigating wire capacitance are described. In one embodiment, a method includes loading, by at least a processor into an electronic memory, an electronic data structure that includes a design of an integrated circuit. The design defines layers of the integrated circuit and connections between structures and wire interconnects in the layers. The example method may also include generating, by at least the processor, a structured topology in the design by successively routing the wire interconnects throughout the layers according to coordinates of the structures in the design and weighted values associated with each of the structures to mitigate wire capacitance of the wire interconnects.

Abstract: Systems, methods, and other embodiments associated with an integrated circuit that includes a plurality of parallel pillar structures is described. In one embodiment, an integrated circuit includes a series of layers. The series of layers include a plurality of pillar metals in each of the series of layers. Pillars within each of the series of layers are oriented to be parallel. Pillars in adjacent layers are aligned to be perpendicular. Each of the plurality of pillar metals is a rectangular segment of metal. The plurality of pillar metals form a reconvergent mesh grid. The series of layers includes a plurality of vias connecting the plurality of parallel pillar metals between the series of layers. Vias of the plurality of vias are located at intersections in the reconvergent mesh grid.

Abstract: Systems, methods, and other embodiments associated with mitigating wire capacitance are described. In one embodiment, a method includes loading, by at least a processor into an electronic memory, an electronic data structure that includes a design of an integrated circuit. The design defines layers of the integrated circuit and connections between structures and wire interconnects in the layers. The example method may also include generating, by at least the processor, a structured topology in the design by successively routing the wire interconnects throughout the layers according to coordinates of the structures in the design and weighted values associated with each of the structures to mitigate wire capacitance of the wire interconnects.

Abstract: Systems, methods, and other embodiments associated with an integrated circuit that includes a plurality of parallel pillar structures is described. In one embodiment, an integrated circuit includes a series of layers. The series of layers include a plurality of pillar metals in each of the series of layers. Pillars within each of the series of layers are oriented to be parallel. Pillars in adjacent layers are aligned to be perpendicular. Each of the plurality of pillar metals is a rectangular segment of metal. The plurality of pillar metals form a reconvergent mesh grid. The series of layers includes a plurality of vias connecting the plurality of parallel pillar metals between the series of layers. Vias of the plurality of vias are located at intersections in the reconvergent mesh grid.

Abstract: Systems, methods, and other embodiments associated with an integrated circuit that includes a plurality of parallel pillar structures is described. In one embodiment, a system includes a design logic configured to analyze a design of an integrated circuit to identify open tracks on each layer by determining a location of structures in each layer of the design. The open tracks are spaces on each layer of the design that are free from structures that obstruct routing the plurality of pillar metals. The system also includes routing logic configured to successively route the plurality of pillar metals in each of the layers of the design based, at least in part, on the parameters and the location of the structures. The routing logic routes pillars of the plurality of pillar metals that are in adjacent layers to be perpendicular and pillar metals that are within a same layer of the design to be parallel.

Abstract: Systems, methods, and other embodiments associated with an integrated circuit that includes a plurality of parallel pillar structures is described. In one embodiment, a system includes a design logic configured to analyze a design of an integrated circuit to identify open tracks on each layer by determining a location of structures in each layer of the design. The open tracks are spaces on each layer of the design that are free from structures that obstruct routing the plurality of pillar metals. The system also includes routing logic configured to successively route the plurality of pillar metals in each of the layers of the design based, at least in part, on the parameters and the location of the structures. The routing logic routes pillars of the plurality of pillar metals that are in adjacent layers to be perpendicular and pillar metals that are within a same layer of the design to be parallel.

Abstract: Methods and systems for flexible and repeatable pre-route generation are described. In one embodiment, a routing selection is received. The routing selection is for a path between at least a first cell and a second cell. The first and second cell are associated with a functional description of an integrated circuit. A floorplan associated with the functional description is modified to create a modified floorplan. The modified floorplan has a physical design change relative to the floorplan. A pre-route is automatically generated based on receipt of the routing selection and the modified floorplan. The pre-route is added to a physical design of the chip to create a pre-routed physical design. Additional methods and systems are disclosed.

Abstract: Methods and systems for flexible and repeatable pre-route generation are described. In one embodiment, a routing selection is received. The routing selection is for a path between at least a first cell and a second cell. The first and second cell are associated with a functional description of an integrated circuit. A floorplan associated with the functional description is modified to create a modified floorplan. The modified floorplan has a physical design change relative to the floorplan. A pre-route is automatically generated based on receipt of the routing selection and the modified floorplan. The pre-route is added to a physical design of the chip to create a pre-routed physical design. Additional methods and systems are disclosed.