Abstract: A latch circuit provides for a reading of a state of an EPROM cell and retains that state after the reading sequence is completed. The memory state of the EPROM is inputted to a NOR gate during a power on reset condition. The output of the NOR gate is fed back through an inverter to the input of the NOR gate, such that when the EPROM is deactivated, the input of the NOR gate is latched to the previous EPROM memory state.

Abstract: An improved architecture for an EPROM PAL utilizing two bit lines is disclosed. The drains of the EPROM cells of a given column of an array are coupled together to a first bit line. The first line is coupled to a sensing circuit. The sources of the EPROM cells are coupled together to a second bit line which is then coupled through a current limiting transistor. The gate of the transistor is coupled to the first bit line to receive a feedback signal for controlling the current on the bit lines. The current limiting feature provides for shorter transition periods between "on" and "off" states which results in an improved speed performance of the device.

Abstract: A tri-port transceiver for receiving, switching and transmitting digital information among its ports. An input to each port is coupled to a multiplexer of each other port, wherein the multiplexer of each other port, wherein the multiplexers provide the switching of signals onto other ports. A buffer and a latch are used to couple each input port signal to the multiplexers, and a driver coupled to the multiplexer provides transmission of the selected signal from the multiplexer. An EPROM based PLA operates as a programmable state machine to generate control signals to the tri-port transceiver. In one embodiment, a programmable output impedance driver is used.