Patents by Inventor Kirill Trunov

Kirill Trunov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240047439
    Abstract: An electronic device includes a substrate including first and second metal regions, a first passive device that includes a metal joining surface and is arranged on the substrate with the metal joining surface of the first passive device facing first metal region, a semiconductor die that includes a metal joining surface and is arranged on the substrate with the metal joining surface of the semiconductor die facing the second metal region, a first soldered joint between the metal joining surface of the first passive device and the first metal region; and a second soldered joint between the metal joining surface of the semiconductor die and the second metal region, wherein a minimum thickness of the first soldered joint is greater than a maximum thickness of the second soldered joint.
    Type: Application
    Filed: September 15, 2023
    Publication date: February 8, 2024
    Inventors: Kirill Trunov, Waltraud Eisenbeil, Frederick Groepper, Joerg Schadewald, Arthur Unrau, Ulrich Wilke
  • Patent number: 11798924
    Abstract: A batch soldering method includes providing a first passive device, arranging the first passive device on a first metal region of a substrate with a region of first solder material between the first passive device and the substrate, providing a semiconductor die, arranging the semiconductor die on a second metal region of the substrate with a region of second solder material between the semiconductor die and the substrate, and performing a common soldering step that simultaneously forms a first soldered joint from the region of first solder material and forms a second soldered joint from the region of second solder material. The common soldering step is performed at a soldering temperature such that one or more intermetallic phases form within the second soldered joint, each of the one or more intermetallic phases having a melting point above the second solder material and the soldering temperature.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: October 24, 2023
    Assignee: Infineon Technologies AG
    Inventors: Kirill Trunov, Waltraud Eisenbeil, Frederick Groepper, Joerg Schadewald, Arthur Unrau, Ulrich Wilke
  • Patent number: 11764185
    Abstract: A method of soldering includes providing a substrate having a first metal joining surface, providing a semiconductor die having a second metal joining surface, providing a solder preform having a first interface surface and a second interface surface, arranging the solder preform between the substrate and the semiconductor die such that the first interface surface faces the first metal joining surface and such that the second interface surface faces the second metal joining surface, and performing a mechanical pressure-free diffusion soldering process that forms a soldered joint between the substrate and the semiconductor die by melting the solder preform and forming intermetallic phases in the solder. One or both of the first interface surface and the second interface surface has a varying surface profile that creates voids between the solder preform and one or both of the substrate and the semiconductor die before the melting of the solder preform.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: September 19, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Kirill Trunov, Thomas Hendrix
  • Publication number: 20230130092
    Abstract: A semiconductor device includes: a semiconductor die having a metal region; a substrate having a metal region; and a soldered joint between the metal region of the semiconductor die and the metal region of the substrate. One or more intermetallic phases are present throughout the entire soldered joint, each of the one or more intermetallic phases formed from a solder preform diffused into the metal region of the semiconductor die and the metal region of the substrate. The soldered joint has the same length-to-width aspect ratio as the semiconductor die.
    Type: Application
    Filed: December 20, 2022
    Publication date: April 27, 2023
    Inventors: Alexander Heinrich, Konrad Roesl, Kirill Trunov, Arthur Unrau
  • Patent number: 11605608
    Abstract: A method of joining a semiconductor die to a substrate includes: applying a solder preform to a metal region of the semiconductor die or to a metal region of the substrate, the solder preform having a maximum thickness of 30 ?m and a lower melting point than both metal regions; forming a soldered joint between the metal region of the semiconductor die and the metal region of the substrate via a diffusion soldering process and without applying pressure directly to the die; and setting a soldering temperature of the diffusion soldering process so that the solder preform melts and fully reacts with the metal region of the semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the melting point of the preform and the soldering temperature.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: March 14, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Alexander Heinrich, Konrad Roesl, Kirill Trunov, Arthur Unrau
  • Publication number: 20230065738
    Abstract: A method of soldering includes providing a substrate having a first metal joining surface, providing a semiconductor die having a second metal joining surface, providing a solder preform having a first interface surface and a second interface surface, arranging the solder preform between the substrate and the semiconductor die such that the first interface surface faces the first metal joining surface and such that the second interface surface faces the second metal joining surface, and performing a mechanical pressure-free diffusion soldering process that forms a soldered joint between the substrate and the semiconductor die by melting the solder preform and forming intermetallic phases in the solder. One or both of the first interface surface and the second interface surface has a varying surface profile that creates voids between the solder preform and one or both of the substrate and the semiconductor die before the melting of the solder preform.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Kirill Trunov, Thomas Hendrix
  • Publication number: 20210391310
    Abstract: A batch soldering method includes providing a first passive device, arranging the first passive device on a first metal region of a substrate with a region of first solder material between the first passive device and the substrate, providing a semiconductor die, arranging the semiconductor die on a second metal region of the substrate with a region of second solder material between the semiconductor die and the substrate, and performing a common soldering step that simultaneously forms a first soldered joint from the region of first solder material and forms a second soldered joint from the region of second solder material. The common soldering step is performed at a soldering temperature such that one or more intermetallic phases form within the second soldered joint, each of the one or more intermetallic phases having a melting point above the second solder material and the soldering temperature.
    Type: Application
    Filed: June 16, 2020
    Publication date: December 16, 2021
    Inventors: Kirill Trunov, Waltraud Eisenbeil, Frederick Groepper, Joerg Schadewald, Arthur Unrau, Ulrich Wilke
  • Publication number: 20210375824
    Abstract: An electronic device includes: a first semiconductor die having a metal region; a substrate having a plurality of metal regions; a first soldered joint between the metal region of the first semiconductor die and a first metal region of the substrate, the first soldered joint having one or more intermetallic phases throughout the entire soldered joint, each of the one or more intermetallic phases formed from a solder preform diffused into the metal region of the first semiconductor die and the first metal region of the substrate; and a second semiconductor die soldered to the first or different metal region of the substrate.
    Type: Application
    Filed: August 16, 2021
    Publication date: December 2, 2021
    Inventors: Kirill Trunov, Alexander Heinrich, Konrad Roesl, Arthur Unrau
  • Patent number: 11158602
    Abstract: A method of batch soldering includes: forming a soldered joint between a metal region of a first semiconductor die and a metal region of a substrate using a solder preform via a soldering process which does not apply pressure directly to the first semiconductor die, the solder preform having a maximum thickness of 30 ?m and a lower melting point than the metal regions; setting a soldering temperature of the soldering process so that the solder preform melts and fully reacts with the metal region of the first semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the preform melting point and the soldering temperature; and soldering a second semiconductor die to the same or different metal region of the substrate, without applying pressure directly to the second semiconductor die.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: October 26, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Kirill Trunov, Alexander Heinrich, Konrad Roesl, Arthur Unrau
  • Publication number: 20210143123
    Abstract: A method of batch soldering includes: forming a soldered joint between a metal region of a first semiconductor die and a metal region of a substrate using a solder preform via a soldering process which does not apply pressure directly to the first semiconductor die, the solder preform having a maximum thickness of 30 ?m and a lower melting point than the metal regions; setting a soldering temperature of the soldering process so that the solder preform melts and fully reacts with the metal region of the first semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the preform melting point and the soldering temperature; and soldering a second semiconductor die to the same or different metal region of the substrate, without applying pressure directly to the second semiconductor die.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 13, 2021
    Inventors: Kirill Trunov, Alexander Heinrich, Konrad Roesl, Arthur Unrau
  • Publication number: 20210143120
    Abstract: A method of joining a semiconductor die to a substrate includes: applying a solder preform to a metal region of the semiconductor die or to a metal region of the substrate, the solder preform having a maximum thickness of 30 ?m and a lower melting point than both metal regions; forming a soldered joint between the metal region of the semiconductor die and the metal region of the substrate via a diffusion soldering process and without applying pressure directly to the die; and setting a soldering temperature of the diffusion soldering process so that the solder preform melts and fully reacts with the metal region of the semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the melting point of the preform and the soldering temperature.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 13, 2021
    Inventors: Alexander Heinrich, Konrad Roesl, Kirill Trunov, Arthur Unrau
  • Patent number: 9741639
    Abstract: A semiconductor chip includes a semiconductor body and a chip metallization applied on the semiconductor body. The chip metallization has an underside facing away from the semiconductor body. The chip further includes a layer stack applied to the underside of the chip metallization and having a number N1?1 or N1?2 of first partial layers and a number N2?2 of second partial layers. The first partial layers and the second partial layers are arranged alternately and successively such that at least one of the second partial layers is arranged between the first partial layers of each first pair of the first partial layers and such that at least one of the first partial layers is arranged between the second partial layers of each second pair of the second partial layers.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: August 22, 2017
    Assignee: Infineon Technologies AG
    Inventors: Frank Umbach, Niels Oeschler, Kirill Trunov
  • Patent number: 8736052
    Abstract: A semiconductor device includes a substrate and a first sintered silver layer on the substrate. The semiconductor device includes a first semiconductor chip and a first diffusion soldered layer coupling the first semiconductor chip to the first sintered silver layer.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: May 27, 2014
    Assignee: Infineon Technologies AG
    Inventors: Niels Oeschler, Kirill Trunov, Roland Speckels
  • Publication number: 20140077376
    Abstract: A semiconductor chip includes a semiconductor body and a chip metallization applied on the semiconductor body. The chip metallization has an underside facing away from the semiconductor body. The chip further includes a layer stack applied to the underside of the chip metallization and having a number N1?1 or N1?2 of first partial layers and a number N2?2 of second partial layers. The first partial layers and the second partial layers are arranged alternately and successively such that at least one of the second partial layers is arranged between the first partial layers of each first pair of the first partial layers and such that at least one of the first partial layers is arranged between the second partial layers of each second pair of the second partial layers.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 20, 2014
    Inventors: Frank Umbach, Niels Oeschler, Kirill Trunov
  • Publication number: 20130049204
    Abstract: A semiconductor device includes a substrate and a first sintered silver layer on the substrate. The semiconductor device includes a first semiconductor chip and a first diffusion soldered layer coupling the first semiconductor chip to the first sintered silver layer.
    Type: Application
    Filed: August 22, 2011
    Publication date: February 28, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Niels Oeschler, Kirill Trunov, Roland Speckels