Patents by Inventor Kiritkumar Panchal

Kiritkumar Panchal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Noise immunity circuitry for phase locked loops and delay locked loops
    Patent number: 7372341
    Abstract: A clock circuit. The clock circuit includes a phase detector and an output unit. The phase detector is coupled to receive a reference clock signal and an output clock signal, and is configured to provide a phase signal indicative of a phase difference between the reference and output clock signals. The output unit is configured to provide the output clock signal, and is coupled to a first supply voltage node and a second supply voltage node. The output unit includes a biasing circuit and a voltage-controlled element. The biasing circuit is coupled to receive a control voltage based on the phase signal and is configured to generate a bias voltage based on the received control voltage. The voltage-controlled element is configured to adjust a parameter of the output clock signal based on the bias voltage. A supply-independent output clock is attained using this configuration.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: May 13, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Kailashnath Nagarakanti, Kiritkumar Panchal, Sung-Hun Oh
  • Noise immunity circuitry for phase locked loops and delay locked loops
    Publication number: 20070247251
    Abstract: A clock circuit. The clock circuit includes a phase detector and an output unit. The phase detector is coupled to receive a reference clock signal and an output clock signal, and is configured to provide a phase signal indicative of a phase difference between the reference and output clock signals. The output unit is configured to provide the output clock signal, and is coupled to a first supply voltage node and a second supply voltage node. The output unit includes a biasing circuit and a voltage-controlled element. The biasing circuit is coupled to receive a control voltage based on the phase signal and is configured to generate a bias voltage based on the received control voltage. The voltage-controlled element is configured to adjust a parameter of the output clock signal based on the bias voltage. A supply-independent output clock is attained using this configuration.
    Type: Application
    Filed: April 25, 2006
    Publication date: October 25, 2007
    Inventors: Kailashnath Nagarakanti, Kiritkumar Panchal, Sung-Hun Oh