Abstract: Apparatus and associated methods relate to mitigating data-stream dropout in a serial data-stream. A time-sequence of messages of the serial data-stream is received, each containing a data packet communicating an action. Validity of each of the time-sequence of messages received is determined. After receiving each valid message, a plurality of future actions is created based at least in part on the valid message received. The plurality of future actions corresponds to a plurality of future data packets of the time-sequence of messages. After receiving each valid message, the action communicated in the valid message received is performed. After receiving each invalid messages, a next one of the set of sequential future actions created is instead used in place of any action communicated in the data packet of the invalid message received.

Abstract: A computing method and device for detecting an anomaly event in a hardware- based machine learning anomaly event detector. Data is received from a plurality of input/output interfaces (I/O) or internal functions, wherein the received data of each I/O is associated with a certain sensor or effector. The received data from the plurality of I/O's is analyzed to determine the occurrence of an anomaly event for data from one of the plurality of I/O's. This analysis includes using machine learning techniques dynamically programmed to detect an anomaly event for the I/O data being analyzed by using predetermined parameter values. The predetermined parameter values are retrieved from memory, and are associated with the I/O data being analyzed.

Abstract: A computing method and device for detecting an anomaly event in a hardware-based machine learning anomaly event detector. Data is received from a plurality of input/output interfaces (I/O) or internal functions, wherein the received data of each I/O is associated with a certain sensor or effector. The received data from the plurality of I/O's is analyzed to determine the occurrence of an anomaly event for data from one of the plurality of I/O's. This analysis includes using machine learning techniques dynamically programmed to detect an anomaly event for the I/O data being analyzed by using predetermined parameter values. The predetermined parameter values are retrieved from memory, and are associated with the I/O data being analyzed.

Abstract: A machine learning system that includes one or more machine learning models implemented in one or more hardware processors, a first-level feature creation module, and a combination module provides an output based on one or more channel inputs. Each of the one or more machine learning models receives the channel inputs and additional feature inputs based on the channel inputs to produce the output. The first-level feature creation module receives the channel inputs, performs a feature creation operation, creates the additional feature inputs, and provides the additional feature inputs to at least one of the machine learning models. The first-level feature creation operation performs a calculation on one or more aspects of the channel inputs, and the combination module receives the one or more machine learning model outputs and produce a machine learning channel output.

Abstract: A speed detection device includes a comparator module, a sensor lead with a node connected to the comparator module, and a limit set module. The limit set module is connected to the sensor lead node and to the comparator by an upper limit lead and a lower limit lead to provide upper and lower limits to the comparator that vary according to amplitude variation in voltage applied to the sensor lead.

Abstract: A machine learning system that includes three machine learning models implemented in a hardware processor, a first-level feature creation module, and a combination module provides an output based on one or more channel inputs. Each of the three machine learning models receives the channel inputs and additional feature inputs based on the channel inputs to produce the output. The first-level feature creation module is implemented in hardware and receives the channel inputs, performs a feature creation operation, creates the additional feature inputs, and provides the additional feature inputs to at least one of the machine learning models. The first-level feature creation operation performs a calculation on one or more aspects of the channel inputs, and the combination module receives the one or more machine learning model outputs and produce a machine learning channel output.

Abstract: A resolver system includes a rotatable primary winding, a secondary winding fixed relative to the rotatable primary winding, a tertiary winding fixed relative to the rotatable primary winding and positioned ?/2 radians out of phase with respect to the fixed secondary winding, an excitation module electrically connected to the rotatable primary winding and configured to provide an excitation signal to the rotatable primary winding where the excitation signal is an alternating current waveform having a fundamental frequency, and a controller electrically connected to the secondary winding and configured to sample a voltage across the secondary winding at 18 times the fundamental frequency, sample a voltage across the tertiary winding at 18 times the fundamental frequency, and determine an amplitude of the fundamental frequency based on the sampled voltages across the secondary and tertiary windings, where the alternating current waveform includes a third harmonic frequency.

Abstract: A machine learning system that includes three machine learning models implemented in a hardware processor, a first-level feature creation module, and a combination module provides an output based on one or more channel inputs. Each of the three machine learning models receives the channel inputs and additional feature inputs based on the channel inputs to produce the output. The first-level feature creation module is implemented in hardware and receives the channel inputs, performs a feature creation operation, creates the additional feature inputs, and provides the additional feature inputs to at least one of the machine learning models. The first-level feature creation operation performs a calculation on one or more aspects of the channel inputs, and the combination module receives the one or more machine learning model outputs and produce a machine learning channel output.

Abstract: A machine learning system that includes one or more machine learning models implemented in one or more hardware processors, a first-level feature creation module, and a combination module provides an output based on one or more channel inputs. Each of the one or more machine learning models receives the channel inputs and additional feature inputs based on the channel inputs to produce the output. The first-level feature creation module receives the channel inputs, performs a feature creation operation, creates the additional feature inputs, and provides the additional feature inputs to at least one of the machine learning models. The first-level feature creation operation performs a calculation on one or more aspects of the channel inputs, and the combination module receives the one or more machine learning model outputs and produce a machine learning channel output.

Abstract: A self-powering tamper detection system architecture includes a power source, a tamper detector configured to identify a tamper event, a tamper switch electrically connected to the power source and mechanically connected to the tamper detector, a tamper controller configured to produce a tamper response when the tamper event is identified, and program memory configured to store program data. The tamper detector is configured to mechanically actuate the tamper switch when a tamper event occurs, and the tamper response provides a disruption of the program data. The tamper detector and the tamper switch can include printed circuit board and embedded transformer, whereby the embedded transformer includes an axially-moveable ferromagnetic core.

Abstract: A self-powering tamper detection system architecture includes a power source, a tamper detector configured to mechanically actuate a tamper switch when a tamper event occurs, a tamper switch electrically connected to the power source and mechanically connected to the tamper detector, a tamper unlock system configured to provide a tamper unlock signal when an authorized maintenance condition exists, a tamper controller configured to produce a tamper response when the tamper event is identified, and to not produce the tamper response when the tamper unlock signal is provided, and program memory configured to store program data. The tamper response produces a disruption of the program data.

Abstract: A speed detection device includes a comparator module, a sensor lead with a node connected to the comparator module, and a limit set module. The limit set module is connected to the sensor lead node and to the comparator by an upper limit lead and a lower limit lead to provide upper and lower limits to the comparator that vary according to amplitude variation in voltage applied to the sensor lead.

Abstract: A power supply system with redundant control includes a power conversion unit configured to provide a regulated output voltage, a first power supply controller configured to control the power conversion unit such that the regulated output voltage is within a selected range, a second power supply controller having power supply controller diversity from the first power supply controller configured to control the power conversion unit such that the regulated output voltage is within a selected range, and a controller selector configured to enable either the first power supply controller or the second power supply controller in response to a control signal from a logic control circuit. The power supply controller diversity can be duty cycle diversity, frequency diversity, power supply requirement diversity, manufacturer diversity, part number diversity, foundry diversity, fabrication batch diversity, and/or manufacturing date diversity.

Abstract: A speed detection device includes a comparator module, a sensor lead with a node connected to the comparator module, and a limit set module. The limit set module is connected to the sensor lead node and to the comparator by an upper limit lead and a lower limit lead to provide upper and lower limits to the comparator that vary according to amplitude variation in voltage applied to the sensor lead.

Abstract: A self-powering tamper detection system architecture includes a power source, a tamper detector configured to mechanically actuate a tamper switch when a tamper event occurs, a tamper switch electrically connected to the power source and mechanically connected to the tamper detector, a tamper unlock system configured to provide a tamper unlock signal when an authorized maintenance condition exists, a tamper controller configured to produce a tamper response when the tamper event is identified, and to not produce the tamper response when the tamper unlock signal is provided, and program memory configured to store program data. The tamper response produces a disruption of the program data.

Abstract: A self-powering tamper detection system architecture includes a power source, a tamper detector configured to identify a tamper event, a tamper switch electrically connected to the power source and mechanically connected to the tamper detector, a tamper controller configured to produce a tamper response when the tamper event is identified, and program memory configured to store program data. The tamper detector is configured to mechanically actuate the tamper switch when a tamper event occurs, and the tamper response provides a disruption of the program data. The tamper detector and the tamper switch can include printed circuit board and embedded transformer, whereby the embedded transformer includes an axially-moveable ferromagnetic core.

Abstract: A modular embedded controller includes an enclosure with an external interface, a generic motherboard, and an external device-specific input/output daughterboard. The generic motherboard has a supervisory processor and a plurality of daughterboard seats and is supported in the enclosure. The external device-specific input/output daughterboard is supported in one of the daughterboard seats, connects the external interface to the motherboard supervisory processor, and has an input/output processor translate data communicated between the motherboard supervisory processor and a device connected to the external interface. Embedded engine controllers and gas turbine engines with embedded controllers are also described.

Abstract: A Joint Test Action Group (JTAG) communication lockout processor is disclosed. The processor is configured to generate a unlock sequence based on an operational mode change of an operably connected programmable device, and save the unlock sequence to one or more memory registers. The processor can also receive an execution of the unlock sequence via a dual function JTAG communication bus, determine, via an unlock logic, whether the execution of the unlock sequence is valid, and responsive to determining that the execution of the unlock sequence is valid, allow or disallow the JTAG communication with an embedded processor.

Abstract: A resolver system includes a rotatable primary winding, a secondary winding fixed relative to the rotatable primary winding, a tertiary winding fixed relative to the rotatable primary winding and positioned ?/2 radians out of phase with respect to the fixed secondary winding, an excitation module electrically connected to the rotatable primary winding and configured to provide an excitation signal to the rotatable primary winding where the excitation signal is an alternating current waveform having a fundamental frequency, and a controller electrically connected to the secondary winding and configured to sample a voltage across the secondary winding at 18 times the fundamental frequency, sample a voltage across the tertiary winding at 18 times the fundamental frequency, and determine an amplitude of the fundamental frequency based on the sampled voltages across the secondary and tertiary windings, where the alternating current waveform includes a third harmonic frequency.

Abstract: A system for detecting a position of a dual solenoid device includes device configured to move between first and second positions, and a controller. The controller has first and second monitoring circuits in operable communication with first and second channels, respectively. The first and second channels are in operable communication with first and second solenoids, respectively. Each solenoid is configured to selectively operate as an active solenoid to move the device when the solenoid and its respective channel are in an active mode, and as a passive solenoid when the solenoid and its respective channel are in a passive mode to passively move with the active solenoid. Each of the monitoring circuits is configured to determine a position of the device when the channel the monitoring circuit is associated with is operating in the passive mode by monitoring an electrical parameter of the passive solenoid associated with that channel.