Patents by Inventor Kirk D. Prall
Kirk D. Prall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240113223Abstract: A transistor comprising threshold voltage control gates. The transistor also comprises active control gates adjacent opposing first sides of a channel region, the threshold voltage control gates adjacent opposing second sides of the channel region, and a dielectric region between the threshold voltage control gates and the channel region and between the active control gates and the channel region. A semiconductor device comprising memory cells comprising the transistor is also disclosed, as are systems comprising the memory cells, methods of forming the semiconductor device, and methods of operating a semiconductor device.Type: ApplicationFiled: December 5, 2023Publication date: April 4, 2024Inventors: Kamal M. Karda, Kirk D. Prall, Haitao Liu, Durai Vishak Nirmal Ramaswamy
-
Patent number: 11853552Abstract: The hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their respective logic storage components. In some examples, the volatile memory cells may be used as a cache for the non-volatile memory cells. Or the non-volatile memory cells may be used as a back-up for the volatile memory cells. By placing both types of cells on a single die, rather than separate dies, various performance metrics may be improved, including those related to power consumption and operation speed.Type: GrantFiled: July 13, 2021Date of Patent: December 26, 2023Assignee: Micron Technology, Inc.Inventors: Kevin J. Ryan, Kirk D. Prall, Durai Vishak Nirmal Ramaswamy, Robert Quinn
-
Patent number: 11843055Abstract: A transistor comprising threshold voltage control gates. The transistor also comprises active control gates adjacent opposing first sides of a channel region, the threshold voltage control gates adjacent opposing second sides of the channel region, and a dielectric region between the threshold voltage control gates and the channel region and between the active control gates and the channel region. A semiconductor device comprising memory cells comprising the transistor is also disclosed, as are systems comprising the memory cells, methods of forming the semiconductor device, and methods of operating a semiconductor device.Type: GrantFiled: October 8, 2019Date of Patent: December 12, 2023Assignee: Micron Technology, Inc.Inventors: Kamal M. Karda, Kirk D. Prall, Haitao Liu, Durai Vishak Nirmal Ramaswamy
-
Patent number: 11744061Abstract: A method of forming an array of capacitors comprises forming a vertical stack above a substrate. The stack comprises a horizontally-elongated conductive structure and an insulator material directly above the conductive structure. Horizontally-spaced openings are formed in the insulator material to the conductive structure. An upwardly-open container-shaped bottom capacitor electrode is formed in individual of the openings. The bottom capacitor electrode is directly against conductive material of the conductive structure. The conductive structure directly electrically couples the bottom capacitor electrodes together. A capacitor insulator is formed in the openings laterally-inward of the bottom capacitor electrodes. A top capacitor electrode is formed in individual of the openings laterally-inward of the capacitor insulator. The top capacitor electrodes are not directly electrically coupled together. Structure independent of method is disclosed.Type: GrantFiled: January 27, 2021Date of Patent: August 29, 2023Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Kirk D. Prall, Mitsunari Sukekawa
-
Patent number: 11706929Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.Type: GrantFiled: December 23, 2021Date of Patent: July 18, 2023Assignee: Micron Technology, Inc.Inventors: Kamal M. Karda, Qian Tao, Durai Vishak Nirmal Ramaswamy, Haitao Liu, Kirk D. Prall, Ashonita Chavan
-
Patent number: 11594611Abstract: Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.Type: GrantFiled: February 19, 2021Date of Patent: February 28, 2023Assignee: Micron Technology, Inc.Inventors: Durai Vishak Ramaswamy, Kirk D. Prall, Wayne Kinney
-
Patent number: 11587615Abstract: The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.Type: GrantFiled: May 10, 2021Date of Patent: February 21, 2023Assignee: Micron Technology, Inc.Inventors: Zengtao T. Liu, Kirk D. Prall
-
Publication number: 20220122998Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.Type: ApplicationFiled: December 23, 2021Publication date: April 21, 2022Applicant: Micron Technology, Inc.Inventors: Kamal M. Karda, Qian Tao, Durai Vishak Nirmal Ramaswamy, Haitao Liu, Kirk D. Prall, Ashonita Chavan
-
Patent number: 11244951Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.Type: GrantFiled: July 13, 2020Date of Patent: February 8, 2022Assignee: Micron Technology, Inc.Inventors: Kamal M. Karda, Qian Tao, Durai Vishak Nirmal Ramaswamy, Haitao Liu, Kirk D. Prall, Ashonita Chavan
-
Publication number: 20210405884Abstract: Methods, systems, and devices for a hybrid memory device are described. The hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their respective logic storage components. In some examples, the volatile memory cells may be used as a cache for the non-volatile memory cells. Or the non-volatile memory cells may be used as a back-up for the volatile memory cells. By placing both types of cells on a single die, rather than separate dies, various performance metrics may be improved, including those related to power consumption and operation speed.Type: ApplicationFiled: July 13, 2021Publication date: December 30, 2021Inventors: Kevin J. Ryan, Kirk D. Prall, Durai Vishak Nirmal Ramaswamy, Robert Quinn
-
Publication number: 20210408294Abstract: A device comprises an array comprising rows and columns of elevationally-extending transistors. An access line interconnects multiple of the elevationally-extending transistors along individual of the rows. The transistors individually comprise an upper source/drain region, a lower source/drain region, and a channel region extending elevationally there-between. The channel region comprises an oxide semiconductor. A transistor gate is operatively laterally-proximate the channel region and comprises a portion of an individual of the access lines. Intra-row-insulating material is longitudinally between immediately-intra-row-adjacent of the elevationally-extending transistors. Inter-row-insulating material is laterally between immediately-adjacent of the rows of the elevationally-extending transistors. At least one of the intra-row-insulating material and the inter-row-insulating material comprises void space. Other embodiments, including method embodiments, are disclosed.Type: ApplicationFiled: September 13, 2021Publication date: December 30, 2021Applicant: Micron Technology, Inc.Inventors: Scott E. Sills, Kirk D. Prall, Durai Vishak Nirmal Ramaswamy, Ramanathan Gandhi
-
Patent number: 11177266Abstract: A method of forming an array of capacitors comprises forming a vertical stack above a substrate. The stack comprises a horizontally-elongated conductive structure and an insulator material directly above the conductive structure. Horizontally-spaced openings are formed in the insulator material to the conductive structure. An upwardly-open container-shaped bottom capacitor electrode is formed in individual of the openings. The bottom capacitor electrode is directly against conductive material of the conductive structure. The conductive structure directly electrically couples the bottom capacitor electrodes together. A capacitor insulator is formed in the openings laterally-inward of the bottom capacitor electrodes. A top capacitor electrode is formed in individual of the openings laterally-inward of the capacitor insulator. The top capacitor electrodes are not directly electrically coupled together. Structure independent of method is disclosed.Type: GrantFiled: August 26, 2019Date of Patent: November 16, 2021Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Kirk D. Prall, Mitsunari Sukekawa
-
Publication number: 20210335420Abstract: The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.Type: ApplicationFiled: May 10, 2021Publication date: October 28, 2021Inventors: Zengtao T. Liu, Kirk D. Prall
-
Patent number: 11152509Abstract: A device comprises an array comprising rows and columns of elevationally-extending transistors. An access line interconnects multiple of the elevationally-extending transistors along individual of the rows. The transistors individually comprise an upper source/drain region, a lower source/drain region, and a channel region extending elevationally there-between. The channel region comprises an oxide semiconductor. A transistor gate is operatively laterally-proximate the channel region and comprises a portion of an individual of the access lines. Intra-row-insulating material is longitudinally between immediately-intra-row-adjacent of the elevationally-extending transistors. Inter-row-insulating material is laterally between immediately-adjacent of the rows of the elevationally-extending transistors. At least one of the intra-row-insulating material and the inter-row-insulating material comprises void space. Other embodiments, including method embodiments, are disclosed.Type: GrantFiled: March 20, 2020Date of Patent: October 19, 2021Assignee: Micron Technology, Inc.Inventors: Scott E. Sills, Kirk D. Prall, Durai Vishak Nirmal Ramaswamy, Ramanathan Gandhi
-
Patent number: 11068166Abstract: A hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their respective logic storage components. In some examples, the volatile memory cells may be used as a cache for the non-volatile memory cells. Or the non-volatile memory cells may be used as a back-up for the volatile memory cells. By placing both types of cells on a single die, rather than separate dies, various performance metrics may be improved, including those related to power consumption and operation speed.Type: GrantFiled: March 19, 2019Date of Patent: July 20, 2021Assignee: Micron Technology, Inc.Inventors: Kevin J. Ryan, Kirk D. Prall, Durai Vishak Nirmal Ramaswamy, Robert Quinn
-
Publication number: 20210175340Abstract: Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.Type: ApplicationFiled: February 19, 2021Publication date: June 10, 2021Applicant: Micron Technology, Inc.Inventors: Durai Vishak Ramaswamy, Kirk D. Prall, Wayne Kinney
-
Publication number: 20210151440Abstract: A method of forming an array of capacitors comprises forming a vertical stack above a substrate. The stack comprises a horizontally-elongated conductive structure and an insulator material directly above the conductive structure. Horizontally-spaced openings are formed in the insulator material to the conductive structure. An upwardly-open container-shaped bottom capacitor electrode is formed in individual of the openings. The bottom capacitor electrode is directly against conductive material of the conductive structure. The conductive structure directly electrically couples the bottom capacitor electrodes together. A capacitor insulator is formed in the openings laterally-inward of the bottom capacitor electrodes. A top capacitor electrode is formed in individual of the openings laterally-inward of the capacitor insulator. The top capacitor electrodes are not directly electrically coupled together. Structure independent of method is disclosed.Type: ApplicationFiled: January 27, 2021Publication date: May 20, 2021Applicant: Micron Technology, Inc.Inventors: Sanh D. Tang, Kirk D. Prall, Mitsunari Sukekawa
-
Patent number: 11004510Abstract: The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.Type: GrantFiled: June 8, 2020Date of Patent: May 11, 2021Assignee: Micron Technology, Inc.Inventors: Zengtao T. Liu, Kirk D. Prall
-
Patent number: 10943986Abstract: Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.Type: GrantFiled: December 29, 2017Date of Patent: March 9, 2021Assignee: Micron Technology, Inc.Inventors: Durai Vishak Ramaswamy, Kirk D. Prall, Wayne Kinney
-
Patent number: 10943915Abstract: Some embodiments include an assembly having a memory cell with an active region which includes a body region between a pair of source/drain regions. A charge-storage material is adjacent to the body region. A conductive gate is adjacent to the charge-storage material. A hole-recharge arrangement is configured to replenish holes within the body region during injection of holes from the body region to the charge-storage material. The hole-recharge arrangement includes a heterostructure active region having at least one source/drain region of a different composition than the body region, and/or includes an extension coupling the body region with a hole-reservoir. A wordline is coupled with the conductive gate. A first comparative digit line is coupled with one of the source/drain regions, and a second comparative digit line is coupled with the other of the source/drain regions.Type: GrantFiled: August 27, 2019Date of Patent: March 9, 2021Assignee: Micron Technology, Inc.Inventors: Kamal M. Karda, Albert Fayrushin, Haitao Liu, Kirk D. Prall