Abstract: In some embodiments, a method, apparatus and system for global shared memory using serial optical memory are presented. In this regard, a memory device is introduced to circulate a signal among a plurality of optical emitters and receivers. Other embodiments are also disclosed and claimed.

Abstract: In some embodiments, a method, apparatus and system for n-dimensional sparse memory using serial optical memory are presented. In this regard, a memory device is introduced to circulate a signal among a plurality of optical emitters and receivers. Other embodiments are also disclosed and claimed.

Abstract: The present disclosure relates to trading computing resources, and more specifically making a market in grid computing resources.

Abstract: A computer system provides an expanded register set by employing transparent register stacks for each general purpose register. Each general purpose register and its corresponding set of auxiliary registers form a register stack. No register identification bits are required in processor instructions to reference auxiliary registers. A register set select storage area is a programmable register provided for the storage of a value that identifies the currently active register level. The register set select storage area is loaded using two additional processor instructions provided as part of the present invention. A register set switch is used for selecting a data path to the register level specified by the register set select storage area. A PUSHREG instruction is used to push the register stack pointer down one level. A POPREG instruction is used to move the register stack pointer up one register level.

Abstract: A cache access controller and method for controlling access to a cache memory are implemented in a computer system having a processor for performing memory access operations specifying an address in main memory, and a cache memory comprised of a number of cache lines. The cache access controller includes a control circuit which produces a number of access values in response to the address, each access value being associated with a cache line and having a true or a false state. The controller also includes an access logic circuit which permits the caching of information associated with the address at a cache line if the access value associated with that cache line is true. An operator register and a parameter register associated with a cache line may be used in conjunction with the address to determine the access value for that cache line using arithmetic, logical, or a combination of arithmetic and logical, functions.

Abstract: A counter for counting instructions is implemented in a computer system having a processor in which instructions are fetched for potential execution. Each instruction is characterized by at least one instruction attribute. The counter includes at least one bit map register for storing a bit map. Each map bit position in the bit map represents a particular instruction attribute. Map bits at predetermined map bit positions are set. A bit mask register stores a bit mask corresponding to a fetched instruction. Each mask bit position in the bit mask represents a particular instruction attribute. A mask bit at a mask bit position is set if the mask bit position represents an instruction attribute of the fetched instruction. Logic circuitry increments a count value associated with a bit map based upon a comparison of the bit map with the bit mask.

Abstract: A computer system is described having selectable pointer validation. The pointer structure is modified to provide selectable pointer validation. Each pointer comprises an effective address portion and a validation enable field. The effective address portion defines the memory location referenced by the pointer. The validation enable field comprises one or more bits of information that indicate whether or not selectable pointer validation is enabled for the particular pointer. Prior to executing a pointer reference, a processor first loads the desired condition of the validation enable field of the pointer. In normal practice of the invention, a programmer would enable selective pointer validation for particular pointers under debug testing or pointers for which a problem may have been encountered. For those pointers for which selective pointer validation is disabled, the pointer reference to the specified effective address occurs without any pointer validation processing.