Patents by Inventor Kirk J. Strozewski
Kirk J. Strozewski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7284231Abstract: A method for improving manufacturability of a design includes performing space or enclosure checks on multiple interacting layers of a layout design and then using the resulting space or enclosure data to move predetermined feature edges in an altered design database to decrease the risk of features widths, feature spaces or feature enclosures being patterned smaller than designed. In some embodiments, the upsized features are larger in the wafer circuit pattern than are drawn in a designed database. The method for improving manufacturability of a design, in some embodiments, is stored on a computer readable storage medium.Type: GrantFiled: December 21, 2004Date of Patent: October 16, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Kevin D. Lucas, Robert E. Boone, Mehul D. Shroff, Kirk J. Strozewski, Chi-Min Yuan, Jason T. Porter
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Patent number: 7176574Abstract: A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.Type: GrantFiled: September 22, 2004Date of Patent: February 13, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Kathleen C. Yu, Kirk J. Strozewski, Janos Farkas, Hector Sanchez, Yeong-Jyh T. Lii
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Patent number: 6858542Abstract: A semiconductor fabrication method that includes forming a film (109) comprising an imaging layer (112) and an under layer (110) over a semiconductor substrate (102). The imaging layer (112) is patterned to produce a printed feature (116) having a printed dimension (124). The under layer (110) is then processed to produce a sloped sidewall void (120) in the under layer (110) wherein the void (120) has a finished dimension (126) in proximity to the underlying substrate that is less than the printed dimension. Processing the under layer (110) may include exposing the wafer to high density low pressure N2 plasma.Type: GrantFiled: January 17, 2003Date of Patent: February 22, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Terry G. Sparks, Ajay Singhal, Kirk J. Strozewski
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Patent number: 6838354Abstract: Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.Type: GrantFiled: December 20, 2002Date of Patent: January 4, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Cindy K. Goldberg, Stanley Michael Filipiak, John C. Flake, Yeong-Jyh T. Lii, Bradley P. Smith, Yuri E. Solomentsev, Terry G. Sparks, Kirk J. Strozewski, Kathleen C. Yu
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Patent number: 6815820Abstract: A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.Type: GrantFiled: May 9, 2002Date of Patent: November 9, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Kathleen C. Yu, Kirk J. Strozewski, Janos Farkas, Hector Sanchez, Yeong-Jyh T. Lii
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Patent number: 6783904Abstract: A method (10) for correcting lithography error includes generating (18) data that defines relationships between at least one predetermined design layout parameter and a known minimum required lithographic process capability (e.g. minimum feature spacing), and then using the data to upsize (30) predetermined isolated features or portions of predetermined isolated or semi-isolated features. In some embodiments, the resulting wafer circuit pattern (70) has isolated features (71, 72, 74) that are all larger than a predetermined minimum width. The upsized features are larger in the wafer circuit pattern (70) than they are drawn in a designed database. The method for correcting the lithography error, in some embodiments, is stored on a computer readable storage medium.Type: GrantFiled: May 17, 2002Date of Patent: August 31, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Kirk J. Strozewski, Kevin D. Lucas, Marc J. Olivares, Chi-Min Yuan
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Publication number: 20040142576Abstract: A semiconductor fabrication method that includes forming a film (109) comprising an imaging layer (112) and an under layer (110) over a semiconductor substrate (102). The imaging layer (112) is patterned to produce a printed feature (116) having a printed dimension (124). The under layer (110) is then processed to produce a sloped sidewall void (120) in the under layer (110) wherein the void (120) has a finished dimension (126) in proximity to the underlying substrate that is less than the printed dimension. Processing the under layer (110) may include exposing the wafer to high density low pressure N2 plasma.Type: ApplicationFiled: January 17, 2003Publication date: July 22, 2004Inventors: Terry G. Sparks, Ajay Singhal, Kirk J. Strozewski
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Publication number: 20040119134Abstract: Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.Type: ApplicationFiled: December 20, 2002Publication date: June 24, 2004Inventors: Cindy K. Goldberg, Stanley Michael Filipiak, John C. Flake, Yeong-Jyh T. Lii, Bradley P. Smith, Yuri E. Solomentsev, Terry G. Sparks, Kirk J. Strozewski, Kathleen C. Yu
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Publication number: 20030213613Abstract: A method (10) for correcting lithography error includes generating (18) data that defines relationships between at least one predetermined design layout parameter and a known minimum required lithographic process capability (e.g. minimum feature spacing), and then using the data to upsize (30) predetermined isolated features or portions of predetermined isolated or semi-isolated features. In some embodiments, the resulting wafer circuit pattern (70) has isolated features (71, 72, 74) that are all larger than a predetermined minimum width. The upsized features are larger in the wafer circuit pattern (70) than they are drawn in a designed database. The method for correcting the lithography error, in some embodiments, is stored on a computer readable storage medium.Type: ApplicationFiled: May 17, 2002Publication date: November 20, 2003Inventors: Kirk J. Strozewski, Kevin D. Lucas, Marc J. Olivares, Chi-Min Yuan
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Publication number: 20030209779Abstract: A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.Type: ApplicationFiled: May 9, 2002Publication date: November 13, 2003Inventors: Kathleen C. Yu, Kirk J. Strozewski, Janos Farkas, Hector Sanchez, Yeong-Jyh T. Lii