Patents by Inventor Kirk M. Bresniker
Kirk M. Bresniker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11650953Abstract: A method of computing in memory, the method including inputting a packet including data into a computing memory unit having a control unit, loading the data into at least one computing in memory micro-unit, processing the data in the computing in memory micro-unit, and outputting the processed data. Also, a computing in memory system including a computing in memory unit having a control unit, wherein the computing in memory unit is configured to receive a packet having data and a computing in memory micro-unit disposed in the computing in memory unit, the computing in memory micro-unit having at least one of a memory matrix and a logic elements matrix.Type: GrantFiled: October 16, 2020Date of Patent: May 16, 2023Assignee: Hewlett Packard Enterprise Development LPInventors: Dejan S. Milojicic, Kirk M. Bresniker, Paolo Faraboschi, John Paul Strachan
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Patent number: 11119941Abstract: According to examples, a system may include a central processing unit (CPU) and a capability enforcement controller in communication with the CPU. The capability enforcement controller may be separate from the CPU and may implement capability processing functions that control capabilities. Capabilities may be defined as unforgeable tokens of authority that protect access by the CPU to a physical address at which the data is stored in a memory.Type: GrantFiled: October 31, 2017Date of Patent: September 14, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Paolo Faraboschi, Dejan S. Milojicic, Kirk M. Bresniker
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Publication number: 20210049125Abstract: A method of computing in memory, the method including inputting a packet including data into a computing memory unit having a control unit, loading the data into at least one computing in memory micro-unit, processing the data in the computing in memory micro-unit, and outputting the processed data. Also, a computing in memory system including a computing in memory unit having a control unit, wherein the computing in memory unit is configured to receive a packet having data and a computing in memory micro-unit disposed in the computing in memory unit, the computing in memory micro-unit having at least one of a memory matrix and a logic elements matrix.Type: ApplicationFiled: October 16, 2020Publication date: February 18, 2021Inventors: Dejan S. Milojicic, Kirk M. Bresniker, Paolo Faraboschi, John Paul Strachan
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Patent number: 10884953Abstract: Example implementations relate to a capability enforcement processor. In an example, a capability enforcement processor may be interposed between a memory that stores data accessible via capabilities and a system processor that executes processes. The capability enforcement processor intercepts a memory request from the system processor and enforces the memory request based on capability enforcement processor capabilities maintained in per-process capability spaces of the capability enforcement processor.Type: GrantFiled: August 31, 2017Date of Patent: January 5, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Dejan S Milojicic, Chris I Dalton, Paolo Faraboschi, Kirk M Bresniker
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Patent number: 10838909Abstract: A method of computing in memory, the method including inputting a packet including data into a computing memory unit having a control unit, loading the data into at least one computing in memory micro-unit, processing the data in the computing in memory micro-unit, and outputting the processed data. Also, a computing in memory system including a computing in memory unit having a control unit, wherein the computing in memory unit is configured to receive a packet having data and a computing in memory micro-unit disposed in the computing in memory unit, the computing in memory micro-unit having at least one of a memory matrix and a logic elements matrix.Type: GrantFiled: September 24, 2018Date of Patent: November 17, 2020Assignee: Hewlett Packard Enterprise Development LPInventors: Dejan S. Milojicic, Kirk M. Bresniker, Paolo Faraboschi, John Paul Strachan
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Publication number: 20200097440Abstract: A method of computing in memory, the method including inputting a packet including data into a computing memory unit having a control unit, loading the data into at least one computing in memory micro-unit, processing the data in the computing in memory micro-unit, and outputting the processed data. Also, a computing in memory system including a computing in memory unit having a control unit, wherein the computing in memory unit is configured to receive a packet having data and a computing in memory micro-unit disposed in the computing in memory unit, the computing in memory micro-unit having at least one of a memory matrix and a logic elements matrix.Type: ApplicationFiled: September 24, 2018Publication date: March 26, 2020Inventors: Dejan S. Milojicic, Kirk M. Bresniker, Paolo Faraboschi, John Paul Strachan
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Publication number: 20190129864Abstract: According to examples, a system may include a central processing unit (CPU) and a capability enforcement controller in communication with the CPU. The capability enforcement controller may be separate from the CPU and may implement capability processing functions that control capabilities. Capabilities may be defined as unforgeable tokens of authority that protect access by the CPU to a physical address at which the data is stored in a memory.Type: ApplicationFiled: October 31, 2017Publication date: May 2, 2019Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventors: Paolo FARABOSCHI, Dejan S. MILOJICIC, Kirk M. BRESNIKER
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Publication number: 20190065408Abstract: Example implementations relate to a capability enforcement processor. In an example, a capability enforcement processor may be interposed between a memory that stores data accessible via capabilities and a system processor that executes processes. The capability enforcement processor intercepts a memory request from the system processor and enforces the memory request based on capability enforcement processor capabilities maintained in per-process capability spaces of the capability enforcement processor.Type: ApplicationFiled: August 31, 2017Publication date: February 28, 2019Inventors: Dejan S Milojicic, Chris I Dalton, Paolo Faraboschi, Kirk M. Bresniker
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Patent number: 9425902Abstract: A system including a driver circuit. The driver circuit is configured to provide first output signals in a first mode for electrical signaling and second output signals in a second mode for optical signaling. The driver circuit is configured to provide the first output signals in the first mode with at least one of a lower frequency and higher power and the second output signals in the second mode with at least one of a higher frequency and lower power.Type: GrantFiled: January 11, 2010Date of Patent: August 23, 2016Assignee: Hewlett Packard Enterprise Development LPInventors: Kirk M. Bresniker, Greg Astfalk
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Patent number: 8347005Abstract: A multi-protocol memory controller includes one or more memory channel controllers. Each of the memory channel controllers coupled to a single channel of DIMM, where the DIMM in each single channel operate according to a specific protocol. A protocol engine is coupled to the memory channel controllers. The protocol engine is configurable to accommodate one or more of the specific protocols. Finally, a system interface is coupled to the protocol engine and is configurable to provide electrical power and signaling appropriate for the specific protocols.Type: GrantFiled: July 31, 2007Date of Patent: January 1, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventor: Kirk M. Bresniker
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Patent number: 8230145Abstract: A memory expansion blade for a multi-protocol architecture, includes dual inline memory modules (DIMMs) and a multi-protocol memory controller coupled to the DIMMs and operable to control operations of the DIMMs. The multi-protocol memory controller includes one or more memory channel controllers, with each of the memory channel controllers coupled to a single channel of DIMM, and where the DIMM in each single channel operate according to a specific protocol. The controller further includes a protocol engine coupled to the memory channel controllers, where the protocol engine is configurable to accommodate one or more of the specific protocols, and a system interface coupled to the protocol engine and configurable to provide electrical power and signaling appropriate for the specific protocols.Type: GrantFiled: July 31, 2007Date of Patent: July 24, 2012Assignee: Hewlett-Packard Development Company, L.P.Inventor: Kirk M. Bresniker
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Publication number: 20120119795Abstract: A system including a driver circuit. The driver circuit is configured to provide first output signals in a first mode for electrical signaling and second output signals in a second mode for optical signaling. The driver circuit is configured to provide the first output signals in the first mode with at least one of a lower frequency and higher power and the second output signals in the second mode with at least one of a higher frequency and lower power.Type: ApplicationFiled: January 11, 2010Publication date: May 17, 2012Inventors: Kirk M Bresniker, Greg Astfalk
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Publication number: 20110093574Abstract: Various embodiments of the present technology, a method [300] of providing a communication pathway within a set of conjoined blades of a blade partition, are described. In one embodiment, an identification of blades within a predefined set of conjoined blades of a blade partition is provided [305]. Configuration information enabling configuring of the blades according to a configuration rule is provided [310]. Subsequent to the configuring of blades, interconnecting configured blades within the blade partition based on the configuration information to establish a communication pathway within the blade partition [315].Type: ApplicationFiled: June 19, 2008Publication date: April 21, 2011Inventors: Loren M. Koehler, Kirk M. Bresniker, Kamran H. Casim
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Patent number: 7519245Abstract: The present invention provides an array of computer cells in which adjacent computer cells communicate over optical pathways.Type: GrantFiled: October 31, 2006Date of Patent: April 14, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kirk M. Bresniker, Richard A. Schumacher
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Publication number: 20090037657Abstract: A memory expansion blade for a multi-protocol architecture, includes dual inline memory modules (DIMMs) and a multi-protocol memory controller coupled to the DIMMs and operable to control operations of the DIMMs. The multi-protocol memory controller includes one or more memory channel controllers, with each of the memory channel controllers coupled to a single channel of DIMM, and where the DIMM in each single channel operate according to a specific protocol. The controller further includes a protocol engine coupled to the memory channel controllers, where the protocol engine is configurable to accommodate one or more of the specific protocols, and a system interface coupled to the protocol engine and configurable to provide electrical power and signaling appropriate for the specific protocols.Type: ApplicationFiled: July 31, 2007Publication date: February 5, 2009Inventor: Kirk M. Bresniker
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Publication number: 20090037641Abstract: A multi-protocol memory controller includes one or more memory channel controllers. Each of the memory channel controllers coupled to a single channel of DIMM, where the DIMM in each single channel operate according to a specific protocol. A protocol engine is coupled to the memory channel controllers. The protocol engine is configurable to accommodate one or more of the specific protocols. Finally, a system interface is coupled to the protocol engine and is configurable to provide electrical power and signaling appropriate for the specific protocols.Type: ApplicationFiled: July 31, 2007Publication date: February 5, 2009Inventor: Kirk M. Bresniker
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Publication number: 20080298742Abstract: The present invention provides an array of computer cells in which adjacent computer cells communicate over optical pathways.Type: ApplicationFiled: October 31, 2006Publication date: December 4, 2008Inventors: Kirk M. Bresniker, Richard A. Schumacher
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Patent number: 7203846Abstract: A system and method intelligently control power consumption of distributed services using a computer system that provides independent computing elements each capable of entering a power saving mode. In accordance with the present invention, three different algorithms are disclosed. The first algorithm is a reduced load power saving algorithm. As the load decreases, duplicate instances of services can be gracefully suspended and the host processor cards hosting these instances can enter a power saving mode. The second algorithm is a priority-based power consumption reduction algorithm. If power consumption must be reduced, services having less of a contribution to revenue are suspended before components that having a higher contribution to revenue. The third algorithm is a minimal power-consuming redundant computing hardware algorithm that allows a “cold spare” host processing card to be pressed into service if another card fails.Type: GrantFiled: October 31, 2001Date of Patent: April 10, 2007Assignee: Hewlett-Packard Development Company, LP.Inventors: Kirk M. Bresniker, Thane M. Larson
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Patent number: 7187546Abstract: The present invention relates to the efficient distribution of equipment for communication modules in a communication networking environment. Where a plurality communication devices serves a networking function, economy of cost and space are obtained by providing equipment and functionality for the individual computing devices from a centralized location such as a base station thereby enabling a simpler and less expensive design for the individual communication devices. The individual computing devices may thereby be made much smaller effecting savings in space at an Internet service provider location. Savings are also obtained by reducing the total number of components required and by reducing the total power consumption of the totality of the hardware in the network. Equipment most amenable to removal from the individual units and centralization in a base station include the main power supply, backup power supply, cooling fans.Type: GrantFiled: September 5, 2003Date of Patent: March 6, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventor: Kirk M. Bresniker
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Patent number: 7187674Abstract: An interconnection architecture allows a digital system to be sold with a switched or ring topology interconnection fabric that can evolve into a point-to-point interconnection fabric as the computer system is expanded, and is capable of supporting high and low end computer systems with a single design. In accordance with the present invention, unique point-to-point interconnections are provided between each pair of modules. In one embodiment, a functional unit is coupled to an adaptive 1-of-N switch, which in turn is coupled to the interconnection fabric to form a switched topology. In a second embodiment, modules are coupled to a full 3×3 switch that fronts an adaptive 2-of-N switch. The second embodiment can be coupled into a ring or switched topology, and can be used to provide additional bandwidth and redundancy.Type: GrantFiled: October 30, 2001Date of Patent: March 6, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventor: Kirk M. Bresniker