Patents by Inventor Kirk Pospesel
Kirk Pospesel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11169848Abstract: A computer implemented method and system for managing power in a 3D chip stack formed of multiple memory layers each having a plurality memory banks and a plurality of Through-Silicon-Vias (TSVs) connecting the memory banks. The TSVs are arranged in a plurality of subsets, each subset of TSVs connecting a corresponding vertical stack of memory banks aligned across a plurality of memory layers. The method includes determining a power delivery budget for each subset of TSVs connecting the corresponding vertical stack of memory banks based on memory requests, keeping track of memory requests to the memory banks of each vertical stack of memory banks and scheduling the memory requests to the memory banks of each vertical stack of memory banks based on the power budget. The memory controller is configured with a scorecard scheduler to manage the memory requests based on the power budget.Type: GrantFiled: January 14, 2020Date of Patent: November 9, 2021Assignee: International Business Machines CorporationInventors: Philip Jacob, James P. Coghlan, Michael Grassi, Kirk Pospesel, Marcel Schaal, Douglas J. Joseph
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Publication number: 20200285512Abstract: A computer implemented method and system for managing power in a 3D chip stack formed of multiple memory layers each having a plurality memory banks and a plurality of Through-Silicon-Vias (TSVs) connecting the memory banks. The TSVs are arranged in a plurality of subsets, each subset of TSVs connecting a corresponding vertical stack of memory banks aligned across a plurality of memory layers. The method includes determining a power delivery budget for each subset of TSVs connecting the corresponding vertical stack of memory banks based on memory requests, keeping track of memory requests to the memory banks of each vertical stack of memory banks and scheduling the memory requests to the memory banks of each vertical stack of memory banks based on the power budget. The memory controller is configured with a scorecard scheduler to manage the memory requests based on the power budget.Type: ApplicationFiled: January 14, 2020Publication date: September 10, 2020Inventors: Philip Jacob, James P. Coghlan, Michael Grassi, Kirk Pospesel, Marcel Schaal, Douglas J. Joseph
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Patent number: 10579425Abstract: A computer implemented method and system for managing power in a 3D chip stack formed of multiple memory layers each having a plurality memory banks and a plurality of Through-Silicon-Vias (TSVs) connecting the memory banks. The TSVs are arranged in a plurality of subsets, each subset of TSVs connecting a corresponding vertical stack of memory banks aligned across a plurality of memory layers. The method includes determining a power delivery budget for each subset of TSVs connecting the corresponding vertical stack of memory banks based on memory requests, keeping track of memory requests to the memory banks of each vertical stack of memory banks and scheduling the memory requests to the memory banks of each vertical stack of memory banks based on the power budget. The memory controller is configured with a scorecard scheduler to manage the memory requests based on the power budget.Type: GrantFiled: October 4, 2018Date of Patent: March 3, 2020Assignee: International Business Machines CorporationInventors: Philip Jacob, James P. Coghlan, Michael Grassi, Kirk Pospesel, Marcel Schaal, Douglas J. Joseph
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Patent number: 10346311Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.Type: GrantFiled: November 7, 2017Date of Patent: July 9, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Luke M. Hopkins, Kirk Pospesel, Gabriel M. Tarr
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Patent number: 10310996Abstract: A system for managing one or more queues in a multi-processor environment includes a memory configured to be accessed by a plurality of processing elements, and a queue manager disposed in communication with a plurality of processors and with the memory, the queue manager configured to control a queue in the memory, the queue including a plurality of queue elements, the queue manager configured to intercept a message from a processing element of the plurality of processing elements and perform one or more queuing operations on the queue based on the message. The system also includes a dynamically configurable queue full value maintained by the queue manager, the queue full value being a threshold value that specifies a maximum number of the queue elements that can be written to before a queue full condition is detected, the maximum number based on a number of processing elements.Type: GrantFiled: May 31, 2017Date of Patent: June 4, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Kirk Pospesel
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Patent number: 10303627Abstract: A system for managing one or more queues in a multi-processor environment includes a memory configured to be accessed by a plurality of processing elements, and a queue manager disposed in communication with a plurality of processors and with the memory, the queue manager configured to control a queue in the memory, the queue including a plurality of queue elements, the queue manager configured to intercept a message from a processing element of the plurality of processing elements and perform one or more queuing operations on the queue based on the message. The system also includes a dynamically configurable queue full value maintained by the queue manager, the queue full value being a threshold value that specifies a maximum number of the queue elements that can be written to before a queue full condition is detected, the maximum number based on a number of processing elements.Type: GrantFiled: November 2, 2017Date of Patent: May 28, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Kirk Pospesel
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Patent number: 10210095Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.Type: GrantFiled: July 6, 2017Date of Patent: February 19, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Luke M. Hopkins, Kirk Pospesel, Gabriel M. Tarr
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Patent number: 10210106Abstract: A system for managing one or more queues in a multi-processor environment includes a queue manager disposed in communication with a plurality of processors and a memory shared by the plurality of processors, and a queue configured to be controlled by the queue manager, the queue including independent and discrete queue elements and having a starting location specified by a base address, the queue manager having one or more dynamically configurable parameters, the one or more dynamically configurable parameters including a size of each of the queue elements. The queue manager is configured to perform receiving a message from a processor of the plurality of processors, the message including an operation address specifying a fixed storage location in the memory and a request related to accessing the memory, selecting the queue based on the operation address, and performing a queuing operation on the queue based on the request.Type: GrantFiled: March 15, 2017Date of Patent: February 19, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven G. Aden, Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Luke M. Hopkins, Kirk Pospesel, Gabriel M. Tarr
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Publication number: 20190012268Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.Type: ApplicationFiled: July 6, 2017Publication date: January 10, 2019Inventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Luke M. Hopkins, Kirk Pospesel, Gabriel M. Tarr
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Publication number: 20190012269Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.Type: ApplicationFiled: November 7, 2017Publication date: January 10, 2019Inventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Luke M. Hopkins, Kirk Pospesel, Gabriel M. Tarr
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Publication number: 20180349300Abstract: A system for managing one or more queues in a multi-processor environment includes a memory configured to be accessed by a plurality of processing elements, and a queue manager disposed in communication with a plurality of processors and with the memory, the queue manager configured to control a queue in the memory, the queue including a plurality of queue elements, the queue manager configured to intercept a message from a processing element of the plurality of processing elements and perform one or more queuing operations on the queue based on the message. The system also includes a dynamically configurable queue full value maintained by the queue manager, the queue full value being a threshold value that specifies a maximum number of the queue elements that can be written to before a queue full condition is detected, the maximum number based on a number of processing elements.Type: ApplicationFiled: November 2, 2017Publication date: December 6, 2018Inventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Kirk Pospesel
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Publication number: 20180349299Abstract: A system for managing one or more queues in a multi-processor environment includes a memory configured to be accessed by a plurality of processing elements, and a queue manager disposed in communication with a plurality of processors and with the memory, the queue manager configured to control a queue in the memory, the queue including a plurality of queue elements, the queue manager configured to intercept a message from a processing element of the plurality of processing elements and perform one or more queuing operations on the queue based on the message. The system also includes a dynamically configurable queue full value maintained by the queue manager, the queue full value being a threshold value that specifies a maximum number of the queue elements that can be written to before a queue full condition is detected, the maximum number based on a number of processing elements.Type: ApplicationFiled: May 31, 2017Publication date: December 6, 2018Inventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Kirk Pospesel
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Publication number: 20180267909Abstract: A system for managing one or more queues in a multi-processor environment includes a queue manager disposed in communication with a plurality of processors and a memory shared by the plurality of processors, and a queue configured to be controlled by the queue manager, the queue including independent and discrete queue elements and having a starting location specified by a base address, the queue manager having one or more dynamically configurable parameters, the one or more dynamically configurable parameters including a size of each of the queue elements. The queue manager is configured to perform receiving a message from a processor of the plurality of processors, the message including an operation address specifying a fixed storage location in the memory and a request related to accessing the memory, selecting the queue based on the operation address, and performing a queuing operation on the queue based on the request.Type: ApplicationFiled: March 15, 2017Publication date: September 20, 2018Inventors: Steven G. Aden, Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Luke M. Hopkins, Kirk Pospesel, Gabriel M. Tarr