Abstract: A complementary bipolar CMOS fabrication method uses a common deposition for both the CMOS gate contacts, and as a sacrificial layer for patterning bipolar devices. The deposition is removed from the bipolar devices and, after implanting base and emitter regions, is replaced with a separate emitter contact. Prior to its removal the sacrificial layer is coated with an oxidation resistant layer that imparts a desirable rounded shape to the edge of a thermal oxide layer that is grown around the bipolar emitter area. Common mask and implant steps are also used to fabricate lightly doped CMOS drains together with bipolar base-link regions, and CMOS source/drain regions together with bipolar external base regions. The fabrication technique also facilitates the fabrication of capacitors with no additional steps required, and includes an improved NiCr resistor contact method.

Abstract: A via (26) is formed through a dielectric layer (8) separating two conductive layers (16,28) by establishing a laterally erodible mask (18) over the dielectric (8), with a window (24) over the desired via location. The mask (18) and exposed dielectric material (8) are eroded simultaneously, preferably by reactive ion etching, producing a via (26) through the dielectric (8) which expands laterally as vertical erosion proceeds. The erosion conditions, the materials for the mask (18) and dielectric (8), and the initial window (24) taper are selected so that the final via (26) is tapered at an angle of less than about 45.degree. to the lower metal layer (6), and preferably about 30.degree.-45.degree., to enable a generally uniform width for the upper metallization (28) in the via (26).