Abstract: An apparatus and method for data processing in a flexible multiple-DSP architecture that can be readily adapted to changing customer demands and changes in DSP processing capability is described. The apparatus comprises of two or more processors, two or more dedicated serial data buses, and a shared data bus. Each processor processes data received via the dedicated data bus in a first type of processing task. Each processor processes data received via the shared data bus in a second type of processing task.

Abstract: A method and apparatus is described that provides for switching active data connections from one processor to another processor without significantly interfering with the transmission of the data. The data may be voice calls and the processors may be DSPs residing on a voice processing module. A DSP resource allocation algorithm may be used to load share the data by selectively moving an active voice call currently being processed on one DSP to another DSP having sufficiently available processing power, without interrupting the prevailing service. The liberated DSP may then be used to process a new active voice call. By using the DSPs to load share, the number of simultaneous active voice calls supported by a voice processing module may be increased.

Abstract: An apparatus and method for data processing in a flexible multiple-DSP architecture that can be readily adapted to changing customer demands and changes in DSP processing capability is described. The apparatus comprises of two or more processors, two or more dedicated serial data buses, and a shared data bus. Each processor processes data received via the dedicated data bus in a first type of processing task. Each processor processes data received via the shared data bus in a second type of processing task.

Abstract: Highly accurate, self-calibrating data processors and methods for calibrating the same use internal analog references with negligible time and temperature drifts. A first input reference signal set generated by any accurate, precision analog reference is applied to a data processor. The corresponding output response is compared to the theoretical ideal output response to determine the data processor's initial gain and offset errors. This information can be stored in non-volatile memory, recalled, and used to compensate for the data processor's initial gain and offset errors during actual use of the data processor. Subsequent errors due to time and temperature drifting can be determined by comparing the output responses to a second input reference signal set which is generated by the internal analog reference. The subsequent errors can be combined with the initial errors to compensate for system errors within the data processor.