Patents by Inventor Kirk Strozewski

Kirk Strozewski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080171285
    Abstract: In an immersion lithography method, the photoresist layer is provided with a shield layer to protect it from degradation caused by contact with the immersion liquid. The shield layer is transparent at the exposure wavelength and is substantially impervious to the immersion liquid. The shield layer can be formed of a material which can be removed using the same developer as is used to develop the photoresist layer after exposure.
    Type: Application
    Filed: February 15, 2005
    Publication date: July 17, 2008
    Applicant: Freescales Semiconductor, Inc.
    Inventors: Kyle Patterson, Kirk Strozewski
  • Publication number: 20060136861
    Abstract: A method for improving manufacturability of a design includes performing space or enclosure checks on multiple interacting layers of a layout design and then using the resulting space or enclosure data to move predetermined feature edges in an altered design database to decrease the risk of features widths, feature spaces or feature enclosures being patterned smaller than designed. In some embodiments, the upsized features are larger in the wafer circuit pattern than are drawn in a designed database. The method for improving manufacturability of a design, in some embodiments, is stored on a computer readable storage medium.
    Type: Application
    Filed: December 21, 2004
    Publication date: June 22, 2006
    Inventors: Kevin Lucas, Robert Boone, Mehul Shroff, Kirk Strozewski, Chi-Min Yuan, Jason Porter
  • Publication number: 20050035459
    Abstract: A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.
    Type: Application
    Filed: September 22, 2004
    Publication date: February 17, 2005
    Inventors: Kathleen Yu, Kirk Strozewski, Janos Farkas, Hector Sanchez, Yeong-Jyh Lii