Patents by Inventor Kirk Yap

Kirk Yap has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10691529
    Abstract: A processing device comprising compression circuitry to: determine a compression configuration to compress source data; generate a checksum of the source data in an uncompressed state; compress the source data into at least one block based on the compression configuration, wherein the at least one block comprises: a plurality of sub-blocks, wherein the plurality of sub-block includes a predetermined size; a block header corresponding to the plurality of sub-blocks; and decompression circuitry coupled to the compression circuitry, wherein the decompression circuitry to: while not outputting a decompressed data stream of the source data: generate index information corresponding to the plurality of sub-blocks; in response to generating the index information, generate a checksum of the compressed source data associated with the plurality of sub-blocks; and determine whether the checksum of the source data in the uncompressed format matches the checksum of the compressed source data.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: June 23, 2020
    Assignee: INTEL CORPORATION
    Inventors: Vinodh Gopal, James Guilford, Daniel Cutter, Kirk Yap
  • Publication number: 20200007329
    Abstract: Disclosed embodiments relate to encrypting or decrypting confidential data with additional authentication data by an accelerator and a processor. In one example, a processor includes processor circuitry to compute a first hash of a first block of data stored in a memory, store the first hash in the memory, and generate an authentication tag based in part on a second hash. The processor further includes accelerator circuitry to obtain the first hash from the memory, decrypt a second block of data using the first hash, and compute the second hash based in part on the first hash and the second block of data.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: James GUILFORD, Vinodh GOPAL, Kirk YAP
  • Publication number: 20200004535
    Abstract: An apparatus and method for loading and storing multiple sets of packed data elements.
    Type: Application
    Filed: June 30, 2018
    Publication date: January 2, 2020
    Inventors: KIRK YAP, JAMES GUILFORD, DANIEL CUTTER, VINODH GOPAL, DANIIL SOKOLOV
  • Publication number: 20190391869
    Abstract: A processing device comprising compression circuitry to: determine a compression configuration to compress source data; generate a checksum of the source data in an uncompressed state; compress the source data into at least one block based on the compression configuration, wherein the at least one block comprises: a plurality of sub-blocks, wherein the plurality of sub-block includes a predetermined size; a block header corresponding to the plurality of sub-blocks; and decompression circuitry coupled to the compression circuitry, wherein the decompression circuitry to: while not outputting a decompressed data stream of the source data: generate index information corresponding to the plurality of sub-blocks; in response to generating the index information, generate a checksum of the compressed source data associated with the plurality of sub-blocks; and determine whether the checksum of the source data in the uncompressed format matches the checksum of the compressed source data.
    Type: Application
    Filed: June 20, 2018
    Publication date: December 26, 2019
    Inventors: Vinodh Gopal, James Guilford, Daniel Cutter, Kirk Yap
  • Publication number: 20190310848
    Abstract: An apparatus and method are described for performing efficient Boolean operations in a pipelined processor which, in one embodiment, does not natively support three operand instructions. For example, in one embodiment, a processor comprises: a set of registers for storing packed operands; Boolean operation logic to execute a single instruction which uses three or more source operands packed in the set of registers, the Boolean operation logic to read at least three source operands and an immediate value to perform a Boolean operation on the three source operands, wherein the Boolean operation comprises: combining a bit read from each of the three operands to form an index to the immediate value, the index identifying a bit position within the immediate value; reading the bit from the identified bit position of the immediate value; and storing the bit from the identified bit position of the immediate value in a destination register.
    Type: Application
    Filed: June 25, 2019
    Publication date: October 10, 2019
    Inventors: Vinodh GOPAL, Wajdi FEGHALI, Gilbert WOLRICH, Kirk YAP
  • Publication number: 20190305797
    Abstract: In one embodiment, an apparatus includes: a compression circuit to compress data blocks of one or more traffic classes; and a control circuit coupled to the compression circuit, where the control circuit is to enable the compression circuit to concurrently compress data blocks of a first traffic class and not to compress data blocks of a second traffic class. Other embodiments are described and claimed.
    Type: Application
    Filed: June 19, 2019
    Publication date: October 3, 2019
    Inventors: Simon N. Peffers, Vinodh Gopal, Kirk Yap
  • Publication number: 20190188132
    Abstract: Various systems and methods for hardware acceleration circuitry are described. In an embodiment, circuitry is to perform 1-bit comparisons of elements of variable M-bit width aligned to N-bit width, where N is a power of 2, in a data path of P-bit width. Second and subsequent scan stages use the comparison results from the previous stage to perform 1-bit comparison of adjacent results, so that each subsequent stage results in a full comparison of element widths double that of the previous stage. A total number of stages required to scan, or filter, M-bit elements in N-bit width lanes is equal 1+log 2(N), and the total number of stages required for implementation in the circuitry is 1+log 2(P), where P is the maximum width of the data path comprising 1 to P elements.
    Type: Application
    Filed: December 18, 2017
    Publication date: June 20, 2019
    Inventors: Kirk Yap, James D. Guilford, Simon N. Peffers, Vinodh Gopal
  • Patent number: 10270464
    Abstract: An apparatus and method for performing efficient lossless compression.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: James Guilford, Kirk Yap, Vinodh Gopal, Daniel Cutter, Wajdi Feghali
  • Publication number: 20190042611
    Abstract: Technologies for determining unique values include a computing device that further includes one or more accelerator devices. Each accelerator device is to receive input data and query configuration data, the input data including a packed array of unsigned integers of column data from a database and the query configuration data including an element width of the input data, and generate, in response to receiving the query configuration data, a bit-map output table based on the query configuration data, generate a write request for each element of the input data to set a corresponding bit-map output bit of the bit-map output table which corresponds to an element value of the corresponding element. Subsequently, the accelerator device is further to set the corresponding bit-map output bit to indicate a presence of the corresponding element and output the bit-map output table indicative of unique elements that are present in the input data.
    Type: Application
    Filed: January 11, 2018
    Publication date: February 7, 2019
    Inventors: Kirk Yap, James Guilford, Daniel Cutter, Vinodh Gopal
  • Publication number: 20190042476
    Abstract: Techniques are described for providing low-overhead cryptographic memory isolation to mitigate attack vulnerabilities in a multi-user virtualized computing environment. Memory read and memory write operations for target data, each operation initiated via an instruction associated with a particular virtual machine (VM), include the generation and/or validation of a message authentication code that is based at least on a VM-specific cryptographic key and a physical memory address of the target data. Such operations may further include transmitting the generated message authentication code via a plurality of ancillary bits incorporated within a data line that includes the target data. In the event of a validation failure, one or more error codes may be generated and provided to distinct trust domain architecture entities based on an operating mode of the associated virtual machine.
    Type: Application
    Filed: June 29, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Siddhartha Chhabra, Rajat Agarwal, Baiju Patel, Kirk Yap
  • Publication number: 20190042475
    Abstract: The disclosed embodiments generally relate to methods, systems and apparatuses to authenticate instructions on a memory circuitry. In an exemplary embodiment, the disclosure relates to a computing device (e.g., a memory protection engine) to protect integrity of one or more memory circuitry.
    Type: Application
    Filed: June 28, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Santosh Ghosh, Kirk Yap, Siddhartha Chhabra
  • Publication number: 20190042481
    Abstract: Systems, methods, and circuitries are disclosed for a per-process memory encryption system. At least one translation lookaside buffer (TLB) is configured to encode key identifiers for keys in one or more bits of either the virtual memory address or the physical address. The process state memory configured to store a first process key table for a first process that maps key identifiers to unique keys and a second process key table that maps the key identifiers to different unique keys. The active process key table memory configured to store an active key table. In response to a request for data corresponding to a virtual memory address, the at least one TLB is configured to provide a key identifier for the data to the active process key table to cause the active process key table to return the unique key mapped to the key identifier.
    Type: Application
    Filed: September 28, 2018
    Publication date: February 7, 2019
    Inventors: Wajdi Feghali, Vinodh Gopal, Kirk Yap, Sean Gulley, Raghunandan Makaram
  • Publication number: 20190045031
    Abstract: Methods and apparatus for low-latency link compression schemes. Under the schemes, selected packets or messages are dynamically selected for compression in view of current transmit queue levels. The latency incurred during compression and decompression is not added to the data-path, but sits on the side of the transmit queue. The system monitors the queue depth and, accordingly, initiates compression jobs based on the depth. Different compression levels may be dynamically selected and used based on queue depth. Under various schemes, either packets or messages are enqueued in the transmit queue or pointers to such packets and messages are enqueued. Additionally, packets/message may be compressed prior to being enqueued, or after being enqueued, wherein an original uncompressed packet is replaced with a compressed packet. Compressed and uncompressed packets may be stored in queues or buffers and transmitted using a different numbers of transmit cycles based on their compression ratios.
    Type: Application
    Filed: June 21, 2018
    Publication date: February 7, 2019
    Inventors: Wajdi Feghali, Vinodh Gopal, Kirk Yap, Sean Gulley, Simon Peffers
  • Publication number: 20190034490
    Abstract: Technologies for determining set membership include a computing device that further includes one or more accelerator devices. Each accelerator device is to receive input data and definition table configuration data, the input data including a packed unsigned integers of column data from database and the definition table configuration data including a set membership query condition, generate a definition table indicative of element values that satisfy the set membership query condition, generate a lookup request for an element of the column data of the input data, perform the lookup request by accessing the definition table to determine whether the element satisfies the set membership query condition, and generate output indicative of whether the element is a member of the set membership.
    Type: Application
    Filed: December 28, 2017
    Publication date: January 31, 2019
    Inventors: Kirk Yap, James Guilford, Daniel Cutter, Vinodh Gopal
  • Patent number: 9503256
    Abstract: Embodiments of an invention for SMS4 acceleration hardware are disclosed. In an embodiment, an apparatus includes SMS4 hardware and key transformation hardware. The SMS4 hardware is to execute a round of encryption and a round of key expansion. The key transformation hardware is to transform a key to provide for the SMS4 hardware to execute a round of decryption.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: November 22, 2016
    Assignee: Intel Corporation
    Inventors: Kirk Yap, Gilbert Wolrich, Sudhir Satpathy, Sean Gulley, Vinodh Gopal, Sanu Mathew, Wajdi Feghali
  • Publication number: 20160191238
    Abstract: Embodiments of an invention for SMS4 acceleration hardware are disclosed. In an embodiment, an apparatus includes SMS4 hardware and key transformation hardware. The SMS4 hardware is to execute a round of encryption and a round of key expansion. The key transformation hardware is to transform a key to provide for the SMS4 hardware to execute a round of decryption.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 30, 2016
    Inventors: Kirk YAP, Gilbert Wolrich, Sudhir Satpathy, Sean Gulley, Vinodh Gopal, Sanu Mathew, Wajdi Feghali
  • Patent number: 9047082
    Abstract: A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: June 2, 2015
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, Shay Gueron, Gilbert Wolrich, Wajdi Feghali, Kirk Yap, Bradley Burres
  • Publication number: 20140229807
    Abstract: A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.
    Type: Application
    Filed: April 16, 2014
    Publication date: August 14, 2014
    Inventors: VINODH GOPAL, SHAY GUERON, GILBERT WOLRICH, WAJDI FEGHALI, KIRK YAP, BRADLEY BURRES
  • Patent number: 8732548
    Abstract: A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: May 20, 2014
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, Shay Gueron, Gilbert Wolrich, Wajdi Feghali, Kirk Yap, Bradley Burres
  • Publication number: 20140095845
    Abstract: An apparatus and method are described for performing efficient Boolean operations in a pipelined processor which, in one embodiment, does not natively support three operand instructions. For example, a processor according to one embodiment of the invention comprises: a set of registers for storing packed operands; Boolean operation logic to execute a single instruction which uses three or more source operands packed in the set of registers, the Boolean operation logic to read at least three source operands and an immediate value to perform a Boolean operation on the three source operands, wherein the Boolean operation comprises: combining a bit read from each of the three operands to form an index to the immediate value, the index identifying a bit position within the immediate value; reading the bit from the identified bit position of the immediate value; and storing the bit from the identified bit position of the immediate value in a destination register.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Vinodh Gopal, Wajdi Feghali, Gilbert Wolrich, Kirk Yap