Patents by Inventor Kirthi Ravindra Kulkarni
Kirthi Ravindra Kulkarni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250259680Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is to perform operations including determining whether a set of memory access operations performed on a first wordline of the memory device satisfies one or more criteria. The operations further include, responsive to determining that the set of memory access operations satisfies the one or more criteria, causing a memory management operation to be performed at the first wordline and a second wordline of the memory device.Type: ApplicationFiled: April 24, 2025Publication date: August 14, 2025Inventors: Laura Varisco, Swetha Bongu, Kirthi Ravindra Kulkarni, Soujanya Venigalla
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Patent number: 12300321Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is to perform operations including determining whether one or more memory access operations performed on a range of consecutive wordlines of a memory device satisfy one or more criteria. The operations further include, responsive to determining that the one or more memory access operations satisfy the one or more criteria, causing a memory management operation to be performed at each wordline of the range of consecutive wordlines of the memory device.Type: GrantFiled: November 2, 2023Date of Patent: May 13, 2025Assignee: Micron Technology, Inc.Inventors: Laura Varisco, Swetha Bongu, Kirthi Ravindra Kulkarni, Soujanya Venigalla
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Publication number: 20240062820Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is to perform operations including determining whether one or more memory access operations performed on a range of consecutive wordlines of a memory device satisfy one or more criteria. The operations further include, responsive to determining that the one or more memory access operations satisfy the one or more criteria, causing a memory management operation to be performed at each wordline of the range of consecutive wordlines of the memory device.Type: ApplicationFiled: November 2, 2023Publication date: February 22, 2024Inventors: Laura Varisco, Swetha Bongu, Kirthi Ravindra Kulkarni, Soujanya Venigalla
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Patent number: 11854600Abstract: A method includes receiving a write request to a write queue of a host having the write queue and a read queue; initiating a write queue timer upon receiving the write request to the write queue of the host, wherein the write queue timer has a write queue timer expiry threshold value; and executing one or more write requests when the write queue timer reaches the write queue timer expiry threshold value.Type: GrantFiled: August 25, 2021Date of Patent: December 26, 2023Assignee: Micron Technology, Inc.Inventors: Nikesh Agarwal, Laurent Isenegger, Kirthi Ravindra Kulkarni
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Patent number: 11817151Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is to perform operations including maintaining a counter to track a number of memory access operations performed on a range of consecutive wordlines in a block of the memory device. The operations further include determining that the number of memory access operations performed on the range of consecutive wordlines satisfies a threshold criterion. The operations further include, responsive to the number of memory access operations performed on the range of consecutive wordlines satisfying the threshold criterion, causing a memory management operation to be performed at each wordline of the range of consecutive wordlines in the block of the memory device.Type: GrantFiled: May 23, 2022Date of Patent: November 14, 2023Assignee: Micron Technology, Inc.Inventors: Laura Varisco, Swetha Bongu, Kirthi Ravindra Kulkarni, Soujanya Venigalla
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Patent number: 11782851Abstract: A method includes determining a traffic pattern of access requests within a queue or a system, or both and dynamically adjusting, within a particular range, a queue depth of the queue based on the determined traffic pattern of access requests to balance bandwidth and latency associated with executing the access requests.Type: GrantFiled: September 1, 2021Date of Patent: October 10, 2023Assignee: Micron Technology, Inc.Inventors: Robert M. Walker, Kirthi Ravindra Kulkarni, Laurent Isenegger
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Publication number: 20230060874Abstract: A method includes determining a traffic pattern of access requests within a queue or a system, or both and dynamically adjusting, within a particular range, a queue depth of the queue based on the determined traffic pattern of access requests to balance bandwidth and latency associated with executing the access requests.Type: ApplicationFiled: September 1, 2021Publication date: March 2, 2023Inventors: Robert M. Walker, Kirthi Ravindra Kulkarni, Laurent Isenegger
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Publication number: 20230065395Abstract: A method includes enqueuing host commands of a first type and a second type in a command queue of a host memory controller and preventing a subsequent host command of the first type from being inserted into the command queue responsive to determining that a quantity of host commands of the first type and enqueued in the command queue having met a criterion.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Robert M. Walker, Kirthi Ravindra Kulkarni, Dhawal Bavishi, Laurent Isenegger
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Publication number: 20230062167Abstract: A method includes receiving a write request to a write queue of a host having the write queue and a read queue; initiating a write queue timer upon receiving the write request to the write queue of the host, wherein the write queue timer has a write queue timer expiry threshold value; and executing one or more write requests when the write queue timer reaches the write queue timer expiry threshold value.Type: ApplicationFiled: August 25, 2021Publication date: March 2, 2023Inventors: Nikesh Agarwal, Laurent Isenegger, Kirthi Ravindra Kulkarni
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Publication number: 20220293181Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is to perform operations including maintaining a counter to track a number of memory access operations performed on a range of consecutive wordlines in a block of the memory device. The operations further include determining that the number of memory access operations performed on the range of consecutive wordlines satisfies a threshold criterion. The operations further include, responsive to the number of memory access operations performed on the range of consecutive wordlines satisfying the threshold criterion, causing a memory management operation to be performed at each wordline of the range of consecutive wordlines in the block of the memory device.Type: ApplicationFiled: May 23, 2022Publication date: September 15, 2022Inventors: Laura Varisco, Swetha Bongu, Kirthi Ravindra Kulkarni, Soujanya Venigalla
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Patent number: 11342024Abstract: A data structure including two or more entries is maintained, where each entry corresponds to a range of consecutive wordlines in a block of a memory device. Each entry includes an operation counter to track a number of memory access operations performed on the range of consecutive wordlines in the block of the memory device. An indication of a memory access operation pertaining to the particular wordline is received. In response to the indication of the memory access operation pertaining to the particular wordline, a determination is made whether the particular wordline is within any range of consecutive wordlines that has a corresponding entry in the data structure. In response to the particular wordline being outside of any range of consecutive wordlines that has a corresponding entry in the data structure, a new entry for a new range of consecutive wordlines that includes the particular wordline is created.Type: GrantFiled: September 14, 2020Date of Patent: May 24, 2022Assignee: Micron Technology, Inc.Inventors: Laura Varisco, Swetha Bongu, Kirthi Ravindra Kulkarni, Soujanya Venigalla
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Publication number: 20210202003Abstract: A data structure including two or more entries is maintained, where each entry corresponds to a range of consecutive wordlines in a block of a memory device. Each entry includes an operation counter to track a number of memory access operations performed on the range of consecutive wordlines in the block of the memory device. An indication of a memory access operation pertaining to the particular wordline is received. In response to the indication of the memory access operation pertaining to the particular wordline, a determination is made whether the particular wordline is within any range of consecutive wordlines that has a corresponding entry in the data structure. In response to the particular wordline being outside of any range of consecutive wordlines that has a corresponding entry in the data structure, a new entry for a new range of consecutive wordlines that includes the particular wordline is created.Type: ApplicationFiled: September 14, 2020Publication date: July 1, 2021Inventors: Laura Varisco, Swetha Bongu, Kirthi Ravindra Kulkarni, Soujanya Venigalla