Abstract: A method and an interfacing circuit are disclosed for transmitting data between a first clock domain operating at a first clock frequency C1 and a second clock domain operating at a second clock frequency C2. In accordance with this invention, data are transmitted from the first domain, through the interfacing circuitry, and to the second domain. Also, the interfacing circuitry includes a synchronization section that operates at a third frequency C3, which, in one embodiment, is greater than and a whole number multiple of C2. Preferably, C3 is an even whole number multiple of C2. In the preferred embodiment, a clock signal A is used to operate the second clock domain at frequency C2, and a clock signal B is used to operate the synchronization section of the interfacing circuitry at frequency C3, and clock signals A and B are source synchronized.

Abstract: A method and an interfacing circuit are disclosed for transmitting data between a first clock domain operating at a first clock frequency C1 and a second clock domain operating at a second clock frequency C2. In accordance with this invention, data are transmitted from the first domain, through the interfacing circuitry, and to the second domain. Also, the interfacing circuitry includes a synchronization section that operates at a third frequency C3, which, in one embodiment, is greater than and a whole number multiple of C2. Preferably, C3 is an even whole number multiple of C2. In the preferred embodiment, a clock signal A is used to operate the second clock domain at frequency C2, and a clock signal B is used to operate the synchronization section of the interfacing circuitry at frequency C3, and clock signals A and B are source synchronized.

Abstract: A method of asynchronously transmitting data from a first clock domain to a second clock domain by transmitting the data from the first domain to a first register; after a first period of time, transmitting the data from the first register to a second register; after a second period of time, transmitting the data from the second register to a third register; and after a third period of time, transmitting the data from the third register to the second clock domain, where the first clock domain operates at a first frequency C1, and the second clock domain operates at a second frequency C2, C1 being faster than C2; and where: the first period of time is determined by C1; and the second and third periods of time are determined by a third frequency C3 that is greater than and a whole number multiple of C2.