Patents by Inventor Kiryung SHIN

Kiryung SHIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11276910
    Abstract: A method for manufacturing a substrate integrated waveguide for a millimeter wave signal is disclosed. In the method, a gold layer is disposed on a top surface of the silicon substrate using a lift-off process. Next, two parallel rows of substantially equal spaced vias are formed in the silicon substrate using a through-silicon-via etching process. Then, a copper layer is disposed on the bottom side of the silicon substrate and on interior surfaces of each via. The separation between the copper layer and the gold layer define a height of the substrate integrated waveguide, while the separation between the two parallel rows of substantially equal spaced vias define a width of the substrate integrated waveguide. In some implementations the length of the substrate defines a length of the substrate integrated waveguide, and the length, width, and height define a resonator that is resonant at a millimeter wave frequency.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: March 15, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Kiryung Shin
  • Publication number: 20200358161
    Abstract: A method for manufacturing a substrate integrated waveguide for a millimeter wave signal is disclosed. In the method, a gold layer is disposed on a top surface of the silicon substrate using a lift-off process. Next, two parallel rows of substantially equal spaced vias are formed in the silicon substrate using a through-silicon-via etching process. Then, a copper layer is disposed on the bottom side of the silicon substrate and on interior surfaces of each via. The separation between the copper layer and the gold layer define a height of the substrate integrated waveguide, while the separation between the two parallel rows of substantially equal spaced vias define a width of the substrate integrated waveguide. In some implementations the length of the substrate defines a length of the substrate integrated waveguide, and the length, width, and height define a resonator that is resonant at a millimeter wave frequency.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Kiryung SHIN
  • Patent number: 10749237
    Abstract: A method for manufacturing a substrate integrated waveguide for a millimeter wave signal is disclosed. In the method, a gold layer is disposed on a top surface of the silicon substrate using a lift-off process. Next, two parallel rows of substantially equal spaced vias are formed in the silicon substrate using a through-silicon-via etching process. Then, a copper layer is disposed on the bottom side of the silicon substrate and on interior surfaces of each via. The separation between the copper layer and the gold layer define a height of the substrate integrated waveguide, while the separation between the two parallel rows of substantially equal spaced vias define a width of the substrate integrated waveguide. In some implementations the length of the substrate defines a length of the substrate integrated waveguide, and the length, width, and height define a resonator that is resonant at a millimeter wave frequency.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: August 18, 2020
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Kiryung Shin
  • Publication number: 20200044303
    Abstract: A method for manufacturing a substrate integrated waveguide for a millimeter wave signal is disclosed. In the method, a gold layer is disposed on a top surface of the silicon substrate using a lift-off process. Next, two parallel rows of substantially equal spaced vias are formed in the silicon substrate using a through-silicon-via etching process. Then, a copper layer is disposed on the bottom side of the silicon substrate and on interior surfaces of each via. The separation between the copper layer and the gold layer define a height of the substrate integrated waveguide, while the separation between the two parallel rows of substantially equal spaced vias define a width of the substrate integrated waveguide. In some implementations the length of the substrate defines a length of the substrate integrated waveguide, and the length, width, and height define a resonator that is resonant at a millimeter wave frequency.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Kiryung SHIN