Patents by Inventor Kiseok Suh

Kiseok Suh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8481426
    Abstract: A method of forming a pattern structure and a method of fabricating a semiconductor device using the pattern structure, are provided the method of forming the pattern structure includes forming a mask on an underlying layer formed on a lower layer. The underlying layer is etched using the mask as an etching mask, thereby forming patterns on the lower layer. The patterns define at least one opening. A sacrificial layer is formed in the opening and the mask is removed. The sacrificial layer in the opening is partially etched when the mask is removed.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: July 9, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-In Kim, Jaehee Oh, Kiseok Suh
  • Publication number: 20120313067
    Abstract: A memory device includes a lower interconnection in a semiconductor substrate, the lower interconnection being made of a material different from the semiconductor substrate, a selection element on the lower interconnection, and a memory element on the selection element.
    Type: Application
    Filed: May 3, 2012
    Publication date: December 13, 2012
    Inventors: Jaekyu LEE, Kiseok Suh, Tae Eung Yoon
  • Publication number: 20120264273
    Abstract: Semiconductor devices and methods of fabricating a semiconductor device are provided. The method includes forming a conductive region in a substrate and forming a dielectric layer on the substrate including the conductive region. The dielectric layer has an opening that exposes the conductive region. A buffer semiconductor pattern having a single crystalline state is formed on the exposed conductive region. A filling semiconductor pattern is formed in the opening using an epitaxial process that employs the single crystalline buffer semiconductor pattern as a seed layer. Related devices are also provided.
    Type: Application
    Filed: March 15, 2012
    Publication date: October 18, 2012
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: YounSeon KANG, Youngkuk Kim, Kiseok Suh
  • Publication number: 20120220087
    Abstract: A variable resistance memory device includes a substrate having a cell array region and a peripheral circuit region, an epitaxial semiconductor layer on the cell array region and the peripheral circuit region, and a peripheral transistor whose channel region is constituted by the epitaxial semiconductor layer on the peripheral circuit region. The peripheral transistor is formed by forming a gate electrode structure on the epitaxial semiconductor layer, and implanting impurities into the epitaxial semiconductor layer to form a source/drain region.
    Type: Application
    Filed: February 15, 2012
    Publication date: August 30, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kiseok SUH
  • Publication number: 20110207285
    Abstract: A method of forming a pattern structure and a method of fabricating a semiconductor device using the pattern structure, are provided the method of forming the pattern structure includes forming a mask on an underlying layer formed on a lower layer. The underlying layer is etched using the mask as an etching mask, thereby forming patterns on the lower layer. The patterns define at least one opening. A sacrificial layer is formed in the opening and the mask is removed. The sacrificial layer in the opening is partially etched when the mask is removed.
    Type: Application
    Filed: February 17, 2011
    Publication date: August 25, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-In Kim, Jaehee Oh, Kiseok Suh