Patents by Inventor Kishalay Haldar
Kishalay Haldar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230095850Abstract: Systems and methods for chip operation using serial peripheral interface (SPI) without a chip select pin are disclosed. A communication link between a host and a device may include a clock line, a host to device line, and a device to host line. The host may signal a start or stop condition using the clock line and the device may send an acknowledgment of the host's signaling through the device to host line. Once acknowledgment is made, the host may then signal on the host to device line using a protocol such as SPI.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Kishalay Haldar, Amit Gil
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Patent number: 11354266Abstract: The systems and methods for hang correction in a power management interface bus cause secondary master devices associated with the power management interface bus to utilize timers to determine if a master that won arbitration has asserted a clock signal within a predefined amount of time. If a timer for a secondary master device expires without a clock signal being asserted by the winning master, the secondary master will assume ownership of the bus and assert a clock signal. Priorities between secondary masters are created by using a master identification (MID) value assigned during bus enumeration to determine a timer value. By allowing the secondary masters to assume ownership after expiration of respective timers, bus ownership is maintained in the event that a winning master hangs and does not assert ownership.Type: GrantFiled: August 19, 2020Date of Patent: June 7, 2022Assignee: QUALCOMM IncorporatedInventors: Sharon Graif, Kishalay Haldar, Navdeep Mer, Viney Kumar, Sriharsha Chakka
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Publication number: 20220058154Abstract: The systems and methods for hang correction in a power management interface bus cause secondary master devices associated with the power management interface bus to utilize timers to determine if a master that won arbitration has asserted a clock signal within a predefined amount of time. If a timer for a secondary master device expires without a clock signal being asserted by the winning master, the secondary master will assume ownership of the bus and assert a clock signal. Priorities between secondary masters are created by using a master identification (MID) value assigned during bus enumeration to determine a timer value. By allowing the secondary masters to assume ownership after expiration of respective timers, bus ownership is maintained in the event that a winning master hangs and does not assert ownership.Type: ApplicationFiled: August 19, 2020Publication date: February 24, 2022Inventors: Sharon Graif, Kishalay Haldar, Navdeep Mer, Viney Kumar, Sriharsha Chakka
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Patent number: 11151068Abstract: A method of improving meta-channel communications over a secure digital (SD) bus between an SD host and an SD client is described. The method includes accessing, during a current data transfer over data lines of the SD bus, a first direct memory access (DMA) metadata and a second DMA metadata over a command (CMD) line of the SD bus using an enhanced SD direct command. The method also includes establishing, prior to a next data transfer over the data lines of the SD bus, a DMA configuration for the next data transfer based on the first DMA metadata and the second DMA metadata. The method further includes communicating the next data transfer over the data lines of the SD bus according to the DMA configuration.Type: GrantFiled: July 21, 2020Date of Patent: October 19, 2021Assignee: QUALCOMM IncorporatedInventor: Kishalay Haldar
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Patent number: 10733121Abstract: Systems, methods, and apparatus for communicating virtual GPIO information generated at multiple source devices and directed to multiple destination devices. A method performed at a device coupled to a serial bus includes generating first virtual GPIO state information representative of state of one or more physical GPIO output pins, asserting a request to transmit the first virtual GPIO state information by driving a data line of the serial bus from a first state to a second state after a start code has been transmitted on a serial bus and before a first clock pulse is transmitted on a clock line of the serial bus, transmitting the first virtual GPIO state information as a first set of bits in a data frame associated with the start code, and receiving second virtual GPIO state information in a second set of bits in the data frame.Type: GrantFiled: April 23, 2019Date of Patent: August 4, 2020Assignee: QUALCOMM IncorporatedInventors: Lalan Jee Mishra, Radu Pitigoi-Aron, Richard Dominic Wietfeldt, Sharon Graif, Lior Amarilio, Kishalay Haldar, Oren Nishry
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Patent number: 10522201Abstract: Aspects of the present disclosure relate to systems and methods for determining a state of a serial memory device. Certain embodiments provide a method of determining a state of a serial memory device. The method includes enabling the serial memory device using a first signal. The method further includes receiving a flag indicating a state of the serial memory device based on the enabling of the serial memory device using the first signal.Type: GrantFiled: May 31, 2018Date of Patent: December 31, 2019Assignee: Qualcomm IncorporatedInventor: Kishalay Haldar
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Publication number: 20190371373Abstract: Aspects of the present disclosure relate to systems and methods for determining a state of a serial memory device. Certain embodiments provide a method of determining a state of a serial memory device. The method includes enabling the serial memory device using a first signal. The method further includes receiving a flag indicating a state of the serial memory device based on the enabling of the serial memory device using the first signal.Type: ApplicationFiled: May 31, 2018Publication date: December 5, 2019Inventor: Kishalay HALDAR
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Publication number: 20190347225Abstract: Systems, methods, and apparatus for communicating virtual GPIO information generated at multiple source devices and directed to multiple destination devices. A method performed at a device coupled to a serial bus includes generating first virtual GPIO state information representative of state of one or more physical GPIO output pins, asserting a request to transmit the first virtual GPIO state information by driving a data line of the serial bus from a first state to a second state after a start code has been transmitted on a serial bus and before a first clock pulse is transmitted on a clock line of the serial bus, transmitting the first virtual GPIO state information as a first set of bits in a data frame associated with the start code, and receiving second virtual GPIO state information in a second set of bits in the data frame.Type: ApplicationFiled: April 23, 2019Publication date: November 14, 2019Inventors: Lalan Jee MISHRA, Radu PITIGOI-ARON, Richard Dominic WIETFELDT, Sharon GRAIF, Lior AMARILIO, Kishalay HALDAR, Oren NISHRY
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Patent number: 10467175Abstract: A method of improving throughput of a secure digital (SD) bus is described. The method includes accessing, during a data transfer over data lines of the SD bus, read metadata over a command (CMD) line of the SD bus between an SD host and an SD client with a first SD direct command. The method also includes reading a read packet over the data lines of the SD bus from the SD client with a second SD direct command. The method further includes storing the read packet in a host buffer allocated according to the read metadata.Type: GrantFiled: November 29, 2018Date of Patent: November 5, 2019Assignee: Qualcomm IncorporatedInventors: Kishalay Haldar, Chandan Pramod Attarde, Yogesh Garhewal
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Patent number: 7002916Abstract: The invention relates, in one embodiment, a computer-implemented method for shaping the output of cells on an output path of a data transmitting device. The data transmitting device is configured for switching the cells from a plurality of input paths to the output path to a network. In one embodiment the method includes sorting a plurality of queues, each queue including a plurality of cells associated with a communication device. The plurality of queues are arranged according to a weight and a data rate associated with each plurality of cells resulting in a plurality of sorted queues of queues. An aggregate output of cells from each sorted queue of queues is regulated based upon the data rates of the queues of the each sorted queue of queues. And, the output of the aggregate output of cells from each sorted queue of queues is regulated based upon the weights of the each sorted queue of queues, such that the scheduled output is coupled to the output path.Type: GrantFiled: January 2, 2001Date of Patent: February 21, 2006Assignees: Conexant Systems, Inc., Raza Microelectronics, Inc.Inventors: Bidyut Parruck, Pramod B. Phadke, Sachin N. Pradhan, Akash Bansal, Kishalay Haldar
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Publication number: 20010001608Abstract: The invention relates, in one embodiment, a computer-implemented method for shaping the output of cells on an output path of a data transmitting device. The data transmitting device is configured for switching the cells from a plurality of input paths to the output path to a network. In one embodiment the method includes sorting a plurality of queues, each queue including a plurality of cells associated with a communication device. The plurality of queues are arranged according to a weight and a data rate associated with each plurality of cells resulting in a plurality of sorted queues of queues. An aggregate output of cells from each sorted queue of queues is regulated based upon the data rates of the queues of the each sorted queue of queues. And, the output of the aggregate output of cells from each sorted queue of queues is regulated based upon the weights of the each sorted queue of queues, such that the scheduled output is coupled to the output path.Type: ApplicationFiled: January 2, 2001Publication date: May 24, 2001Inventors: Bidyut Parruck, Pramod B. Phadke, Sachin N. Pradhan, Akash Bansal, Kishalay Haldar
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Patent number: 6198723Abstract: The invention relates, in one embodiment, a computer-implemented method for shaping the output of cells on an output path of a data transmitting device. The data transmitting device is configured for switching the cells from a plurality of input paths to the output path to a network. In one embodiment the method includes sorting a plurality of queues, each queue including a plurality of cells associated with a communication device. The plurality of queues are arranged according to a weight and a data rate associated with each plurality of cells resulting in a plurality of sorted queues of queues. An aggregate output of cells from each sorted queue of queues is regulated based upon the data rates of the queues of the each sorted queue of queues. And, the output of the aggregate output of cells from each sorted queue of queues is regulated based upon the weights of the each sorted queue of queues, such that the scheduled output is coupled to the output path.Type: GrantFiled: April 14, 1998Date of Patent: March 6, 2001Assignee: Paxonet Communications, Inc.Inventors: Bidyut Parruck, Pramod B. Phadke, Sachin N. Pradhan, Akash Bansal, Kishalay Haldar