Abstract: In an example, an apparatus includes an error amplifier, a buffer, a transistor, and a current-mode feedforward ripple canceller (CFFRC). The error amplifier has an amplifier output, a first input, and a second input, the error amplifier second input configured to receive a reference voltage. The buffer has a buffer input and a buffer output, the buffer input coupled to the error amplifier output. The transistor has a gate, a source, and a drain, the gate coupled to the buffer output, the drain coupled to the first input. The transistor is configured to receive an input voltage (VIN) at the source and provide an output voltage at the drain. The CFFRC has a CFFRC input and a CFFRC output, the CFFRC output coupled to the gate, and the CFFRC input configured to receive VIN.

Abstract: In an example, an apparatus includes an error amplifier, a buffer, a transistor, and a current-mode feedforward ripple canceller (CFFRC). The error amplifier has an amplifier output, a first input, and a second input, the error amplifier second input configured to receive a reference voltage. The buffer has a buffer input and a buffer output, the buffer input coupled to the error amplifier output. The transistor has a gate, a source, and a drain, the gate coupled to the buffer output, the drain coupled to the first input. The transistor is configured to receive an input voltage (VIN) at the source and provide an output voltage at the drain. The CFFRC has a CFFRC input and a CFFRC output, the CFFRC output coupled to the gate, and the CFFRC input configured to receive VIN.

Abstract: In an example, an apparatus includes an error amplifier, a buffer, a transistor, and a current-mode feedforward ripple canceller (CFFRC). The error amplifier has an amplifier output, a first input, and a second input, the error amplifier second input configured to receive a reference voltage. The buffer has a buffer input and a buffer output, the buffer input coupled to the error amplifier output. The transistor has a gate, a source, and a drain, the gate coupled to the buffer output, the drain coupled to the first input. The transistor is configured to receive an input voltage (VIN) at the source and provide an output voltage at the drain. The CFFRC has a CFFRC input and a CFFRC output, the CFFRC output coupled to the gate, and the CFFRC input configured to receive VIN.

Abstract: In an example, an apparatus includes an error amplifier, a buffer, a transistor, and a current-mode feedforward ripple canceller (CFFRC). The error amplifier has an amplifier output, a first input, and a second input, the error amplifier second input configured to receive a reference voltage. The buffer has a buffer input and a buffer output, the buffer input coupled to the error amplifier output. The transistor has a gate, a source, and a drain, the gate coupled to the buffer output, the drain coupled to the first input. The transistor is configured to receive an input voltage (VIN) at the source and provide an output voltage at the drain. The CFFRC has a CFFRC input and a CFFRC output, the CFFRC output coupled to the gate, and the CFFRC input configured to receive VIN.

Abstract: Aspects of the disclosure provide for a circuit. In at least some examples, the circuit comprises a first amplifier, a voltage divider, a first resistor, and a transistor. The first amplifier comprises a first input terminal configured to receive a first voltage signal, a second input terminal coupled to a first node, and an output terminal. The voltage divider is coupled between a second node and a ground node and having the first node as an output node of the voltage divider. The first resistor is coupled at a first end to the second node. The transistor comprises a gate terminal coupled to the output terminal of the first amplifier, the transistor being coupled between an input voltage node and a second end of the first resistor.

Abstract: In an example, an apparatus includes an error amplifier, a buffer, a transistor, and a current-mode feedforward ripple canceller (CFFRC). The error amplifier has an amplifier output, a first input, and a second input, the error amplifier second input configured to receive a reference voltage. The buffer has a buffer input and a buffer output, the buffer input coupled to the error amplifier output. The transistor has a gate, a source, and a drain, the gate coupled to the buffer output, the drain coupled to the first input. The transistor is configured to receive an input voltage (VIN) at the source and provide an output voltage at the drain. The CFFRC has a CFFRC input and a CFFRC output, the CFFRC output coupled to the gate, and the CFFRC input configured to receive VIN.

Abstract: Aspects of the disclosure provide for a circuit. In at least some examples, the circuit comprises a first amplifier, a voltage divider, a first resistor, and a transistor. The first amplifier comprises a first input terminal configured to receive a first voltage signal, a second input terminal coupled to a first node, and an output terminal. The voltage divider is coupled between a second node and a ground node and having the first node as an output node of the voltage divider. The first resistor is coupled at a first end to the second node. The transistor comprises a gate terminal coupled to the output terminal of the first amplifier, the transistor being coupled between an input voltage node and a second end of the first resistor.