Abstract: Systems and methods are described for the measurement of time delay, time delay variation and cell transfer rate in asynchronous transfer mode networks. A method includes generating a time-stamp information cell at a first location; transmitting the time-stamp information cell to a second location via a network link; and receiving the time-stamp information cell at the second location. An apparatus includes an asynchronous transfer mode network including a time delay information cell generator.

Abstract: Systems and methods are described for multi-link segmentation and reassembly for bonging multiple virtual circuits in an inverse multiplexing arrangement. A method includes: generating a plurality of multilink segmentation and reassembly sublayer cells at a first location; distributing the plurality of multilink segmentation and reassembly sublayer cells across a plurality of virtual circuits; transmitting the plurality of multilink segmentation and reassembly sublayer cells to a second location via the plurality of virtual circuits; and receiving the plurality of multilink segmentation and reassembly sublayer cells at the second location. An apparatus includes a multilink segmentation and reassembly sublayer transmitter, including: a source buffer; a multilink controller coupled to the source buffer; and a plurality of virtual circuits coupled to the multilink controller.

Abstract: Systems and methods are described for multi-link segmentation and reassembly for bonging multiple virtual circuits in an inverse multiplexing arrangement. A method includes: generating a plurality of multilink segmentation and reassembly sublayer cells at a first location; distributing the plurality of multilink segmentation and reassembly sublayer cells across a plurality of virtual circuits; transmitting the plurality of multilink segmentation and reassembly sublayer cells to a second location via the plurality of virtual circuits; and receiving the plurality of multilink segmentation and reassembly sublayer cells at the second location. An apparatus includes a multilink segmentation and reassembly sublayer transmitter, including: a source buffer; a multilink controller coupled to the source buffer; and a plurality of virtual circuits coupled to the multilink controller.

Abstract: Systems and methods are described for long subscriber loops using modified load coils.

Abstract: Systems and methods are described for long subscriber loops using automatic gain control. A method includes extending a digital subscriber loop including: producing an output signal from said first variable gain amplifier responsive to an input signal from said digital subscriber loop; monitoring a signal strength of said output signal; generating a gain control signal responsive to said signal strength; and controlling a gain of said variable gain amplifier responsive to said gain control signal. An apparatus includes a digital subscriber loop extender circuit including: a variable gain amplifier having a gain and providing an output signal in response to an input signal from a signal generator over a transmission medium, said output signal having a signal strength as a function of said gain; and a controller coupled to said variable gain amplifier, said controller generating a gain control signal that is feed back to said variable gain amplifier to automatically control said gain.

Abstract: Systems and methods are described for subscriber loop range extension using negative-impedance repeaters. A method includes: extracting a signal from a digital subscriber loop; then amplifying the signal utilizing a negative impedance converter; and then inserting the signal back into the digital subscriber loop. An apparatus includes a negative impedance converter; a downstream high-pass filter electrically coupled to both i) a digital subscriber loop and ii) the negative impedance converter; and an upstream high-pass filter electrically coupled to both i) the negative impedance converter and ii) the digital subscriber loop.

Abstract: Systems and methods are described for a GPS receiver capable of functioning in the presence of interference. A method includes detecting an interfering signal including: tuning a band pass filter over a frequency range; and at each of a plurality of incremental frequencies: computing a set of band pass filter coefficients; sending the set of band pass filter coefficients to a digital filter; repeatedly transforming an analog-to-digital converter output having a quantization level in excess of 2 bits into a band pass filter output with the digital filter to obtain a plurality of samples; computing an average of the plurality of samples; and comparing the average to a threshold to detect peaks that exceed a threshold.

Abstract: Systems and methods are described for clock recovery and detection of rapid phase transients.

Abstract: Systems and methods are described for asymmetric digital subscriber loops.

Abstract: New methods for synchronizing previously unsynchronized BTS's of time division multiple access cellular networks are disclosed. Timing information that is readily available throughout the network is used to determine for each BTS when information representing a particular event is transmitted relative to the timing information. The time differences that are detected are used for steering the clock of each BTS to have the next or some other subsequent event transmitted at the same time.

Abstract: Apparatus and methods for distributing synchronization throughout a network is disclosed. The distribution of the synchronization is through the use of generating a reference timing signal, and by counting the line clock pulses between the start of a frame and the timing reference signal pulse at a first office and that count is then encoded and transmitted to the next office. At the next office, the transmitted count is decoded and used for regenerating synchronization by counting a number of received line clock pulses from the start of the frame to regenerate the reference timing signal. Particular criteria for selecting the frequencies for the timing reference signal are disclosed.

Abstract: Disclosed is a three-way call detection system that uses digital signal processing to identify a third party connection. The disclosed invention operates by establishing a baseline ambient, or background, noise level, and detecting when the signal noise level drops below the ambient noise level. When the current signal noise level drops below the ambient noise level, the system assumes that a three-way conference call has been attempted by the called party.

Abstract: Demodulating FM signals using digital signal processing extracts a carrier signal from digitized channel signals, multiplies the digital channel signal with this extracted carrier signal, and further filters out the carrier signal to produce the demodulated signal. The DSP technique first down converts a group of channels to baseband which are then processed through an A/D converter to produce a digitized composite signal. A bank of bandpass filters, typically based on FFT processors, applied to the composite signal produce (a group of) digitized channel signal(s). The digitized channel signal is then demodulated by recovering a carrier signal by digitally filtering, for example, using a Hilbert bandpass filter, the channel signal and digitally filtering the product of the carrier signal and the channel signal to recover the modulating voice signals.

Abstract: Apparatus and methods for distributing synchronization throughout a network is disclosed. The distribution of the synchronization is through the use of generating a reference timing signal, and by counting the line clock pulses between the start of a frame and the timing reference signal pulse at a first office and that count is then encoded and transmitted to the next office. At the next office, the transmitted count is decoded and used for regenerating synchronization by counting a number of received line clock pulses from the start of the frame to regenerate the reference timing signal. Particular criteria for selecting the frequencies for the timing reference signal are disclosed.

Abstract: An echo canceler (10) is controlled and operated during hangover time between a double talk condition and a single talk condition for a more natural residual echo cancellation. The adaptive gain and the residual suppression threshold necessary for controlling an adaptive filter and a residual echo suppressor, respectively, are computed such that their respective values increase gradually and smoothly from predetermined minimum values to predetermined maximum values during the hangover time.

Abstract: An N:1 data compression system for compressing data on N DS1 trunks carrying 4N channels is disclosed. Waveform encoding circuitry is coupled to the N DS1 trunks for compressing the DS1 data into x bits and producing both encoded data and control parameters, where x.ltoreq.8. The system further includes circuitry coupled to the waveform encoding circuitry for receiving the encoded data and control parameters, performing digital speech interpolation and producing data packets which may include encoded data and control parameters that are transmittable on a single DS1 trunk.

Abstract: A circuit is provided for detecting out-of-lock condition in a phase lock loop. The phase lock loop receives a first signal having a first frequency and a voltage controlled oscillator of the phase lock loop produces a second signal having a second frequency. The circuit comprises a first data flip-flop coupled to the phase lock loop for receiving the first signal and clocked by the second signal. The first flip-flop produces an inverted output of the first signal. A second flip-flop is coupled to the phase lock loop for receiving the second signal clocked by the first signal, and produces a non-inverted output of the second signal. Additionally, an EXCLUSIVE-OR gate is coupled to the first and second flip-flops for receiving the inverted and non-inverted output thereof and producing a signal indicative of an out-of-lock condition.

Abstract: Apparatus for packing and unpacking DS1 trunks comprises a packing circuitry for receiving compressed data from a plurality of DS1 trunks, packing the compressed data into the space of one DS1 trunk, and providing a serial output of data for the packed DS1 trunk. An unpacking circuitry is further provided for receiving data from a packed DS1 trunk, unpacking the data into the space of a plurality of DS1 trunks, and providing an output thereof.

Abstract: An integrated echo canceling multiplexor is provided which comprises an echo canceler for receiving DS1 signals for canceling echo in the DS1 signal and producing an echo-free digital logic signal. A first performance monitor is coupled to the echo canceler for receiving the echo-free digital logic signal and determining the quality of the signal. A multiplexor-demultiplexor is further coupled to the echo canceler for receiving the echo-free digital logic signal and producing a DS3 signal. Additionally, a second performance monitor is coupled to the multiplexor-demultiplexor and receives the DS3 signal and determines the quality of the signal.

Abstract: Rudimentary digital speech interpolation apparatus for compressing data on a plurality of channels is disclosed, which includes circuitry for receiving data bits and control bits for each channel. The presence of silence on each channel is determined in response to the received data bits and zero bits are allocated for any silent channel in a frame structure. In addition, circuitry also allocates x bits per channel for the data bits in an non-silent channel in the frame. At least six bits per channel are also allocated for the control bits in the frame. 4N such frames are grouped to form a multi-frame.