Patents by Inventor Kishnu K. Agarwal

Kishnu K. Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Etch stop layer in poly-metal structures
    Patent number: 7297623
    Abstract: In accordance with one embodiment of the present invention, a method of interfacing a poly-metal structure and a semiconductor substrate is provided where an etch stop layer is provided in a polysilicon region of the structure. The present invention also addresses the relative location of the etch stop layer in the polysilicon region and a variety of structure materials and oxidation methods.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: November 20, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Kishnu K. Agarwal
  • Self-aligned poly-metal structures
    Patent number: 7078327
    Abstract: A semiconductor structure is provided comprising a self-aligned poly-metal stack formed over a semiconductor substrate where the interface between an oxidation barrier placed over the stack and an oxidized portion of the stack lies along the sidewall of the poly-metal stack. A semiconductor structure is also provided where an etch stop layer is present in the poly region of the poly-metal stack. The present invention also relates more broadly to a memory cell array and a computer system including the poly-metal stack of the present invention.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: July 18, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Kishnu K. Agarwal
  • Etch stop layer in poly-metal structures
    Patent number: 6875679
    Abstract: In accordance with one embodiment of the present invention, a method of interfacing a poly-metal stack and a semiconductor substrate is provided where an etch stop layer is provided in a polysilicon region of the stack. The present invention also addresses the relative location of the etch stop layer in the polysilicon region and a variety of stack materials and oxidation methods. The etch stop layer may be patterned within the poly or may be a continuous conductive etch stop layer in the poly. The present invention also relates more broadly to a process for forming wordline architecture of a memory cell. In accordance with another embodiment of the present invention, a semiconductor structure is provided comprising a poly-metal stack formed over a semiconductor substrate where the interface between an oxidation barrier placed over the stack and an oxidized portion of the stack lies along the sidewall of the poly.
    Type: Grant
    Filed: May 14, 2003
    Date of Patent: April 5, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Kishnu K. Agarwal
  • Etch stop layer in poly-metal structures
    Patent number: 6699777
    Abstract: In accordance with one embodiment of the present invention, a method of interfacing a poly-metal stack and a semiconductor substrate is provided where an etch stop layer is provided in a polysilicon region of the stack. The present invention also addresses the relative location of the etch stop layer in the polysilicon region and a variety of stack materials and oxidation methods. The etch stop layer may be patterned within the poly or may be a continuous conductive etch stop layer in the poly. The present invention also relates more broadly to a process for forming wordline architecture of a memory cell. In accordance with another embodiment of the present invention, a semiconductor structure is provided comprising a poly-metal stack formed over a semiconductor substrate where the interface between an oxidation barrier placed over the stack and an oxidized portion of the stack lies along the sidewall of the poly.
    Type: Grant
    Filed: October 4, 2001
    Date of Patent: March 2, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Kishnu K. Agarwal
  • Self-aligned poly-metal structures
    Publication number: 20040021161
    Abstract: A semiconductor structure is provided comprising a self-aligned poly-metal stack formed over a semiconductor substrate where the interface between an oxidation barrier placed over the stack and an oxidized portion of the stack lies along the sidewall of the poly-metal stack. A semiconductor structure is also provided where an etch stop layer is present in the poly region of the poly-metal stack. The present invention also relates more broadly to a memory cell array and a computer system including the poly-metal stack of the present invention.
    Type: Application
    Filed: August 1, 2003
    Publication date: February 5, 2004
    Inventor: Kishnu K. Agarwal