Patents by Inventor Kishor A. Desai

Kishor A. Desai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10319673
    Abstract: An interconnection component includes a first support portion, a second support portion, a redistribution layer and a passive device, wherein at least one of the first and second support portions is comprised of a semiconductor material. The first support portion includes first and second opposed major surfaces and a plurality of first conductive vias extending through the first support portion substantially perpendicular to major surfaces. The second support portion includes first and second opposed major surfaces and a plurality of second conductive vias extending through the second support portion substantially perpendicular to the first and second major surfaces of the second support. The redistribution layer can be disposed between the second surfaces of the first and second support portions. The passive device can be positioned at least partially within the redistribution layer and electrically connected with one or more of the first conductive vias and the second conductive vias.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 11, 2019
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Kishor Desai
  • Publication number: 20180082935
    Abstract: An interconnection component includes a first support portion, a second support portion, a redistribution layer and a passive device, wherein at least one of the first and second support portions is comprised of a semiconductor material. The first support portion includes first and second opposed major surfaces and a plurality of first conductive vias extending through the first support portion substantially perpendicular to major surfaces. The second support portion includes first and second opposed major surfaces and a plurality of second conductive vias extending through the second support portion substantially perpendicular to the first and second major surfaces of the second support. The redistribution layer can be disposed between the second surfaces of the first and second support portions. The passive device can be positioned at least partially within the redistribution layer and electrically connected with one or more of the first conductive vias and the second conductive vias.
    Type: Application
    Filed: November 29, 2017
    Publication date: March 22, 2018
    Inventors: Belgacem Haba, Kishor Desai
  • Patent number: 9875955
    Abstract: A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: January 23, 2018
    Assignee: Tessera, Inc.
    Inventors: Kishor Desai, Qwai H. Low, Chok J. Chia, Charles G. Woychik, Huailiang Wei
  • Patent number: 9837344
    Abstract: An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent a first surface and a second end adjacent a second surface. A second support portion has a plurality of second conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent the first surface and a second end adjacent the second surface. A redistribution layer is disposed between the second surfaces of the first and second support portions, electrically connecting at least some of the first vias with at least some of the second vias. The first and second support portions can have a coefficient of thermal expansion (“CTE”) of less than 12 parts per million per degree, Celsius (“ppm/° C.”).
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: December 5, 2017
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Kishor Desai
  • Patent number: 9670144
    Abstract: The present invention relates to a novel process for preparation of 2-Cyano-3,3-diarylacrylates by the Knoevenagel condensation of Cyanoacetic esters and Arylketones using ammonium compound and acetic acid and without the use of organic solvent.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: June 6, 2017
    Assignee: Galaxy Surfactants, Ltd.
    Inventors: Bharat Bhikaji Parab, Rushit Ramakant Mhatre, Anchita Ravinder Tanwar, Archana Kishor Desai
  • Publication number: 20170077018
    Abstract: A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.
    Type: Application
    Filed: November 28, 2016
    Publication date: March 16, 2017
    Inventors: Kishor DESAI, Qwai H. LOW, Chok J. CHIA, Charles G. WOYCHIK, Huailiang WEI
  • Publication number: 20170053857
    Abstract: An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent a first surface and a second end adjacent a second surface. A second support portion has a plurality of second conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent the first surface and a second end adjacent the second surface. A redistribution layer is disposed between the second surfaces of the first and second support portions, electrically connecting at least some of the first vias with at least some of the second vias. The first and second support portions can have a coefficient of thermal expansion (“CTE”) of less than 12 parts per million per degree, Celsius (“ppm/° C.”).
    Type: Application
    Filed: July 25, 2016
    Publication date: February 23, 2017
    Inventors: Belgacem Haba, Kishor Desai
  • Patent number: 9575266
    Abstract: An opto-electronic assembly is provided comprising a substrate (generally of silicon or glass) for supporting a plurality of interconnected optical and electrical components. A layer of sealing material is disposed to outline a defined peripheral area of the substrate. A molded glass lid is disposed over and bonded to the substrate, where the molded glass lid is configured to create a footprint that matches the defined peripheral area of the substrate. The bottom surface of the molded glass lid includes a layer of bonding material that contacts the substrate's layer of sealing material upon contact, creating a bonded assembly. In one form, a wafer level assembly process is proposed where multiple opto-electronic assemblies are disposed on a silicon wafer and multiple glass lids are molded in a single sheet of glass that is thereafter bonded to the silicon wafer.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: February 21, 2017
    Assignee: Cisco Technology, Inc.
    Inventors: Kishor Desai, Ravinder Kachru, Vipulkumar Patel, Bipin Dama, Kalpendu Shastri, Soham Pathak
  • Patent number: 9557499
    Abstract: Techniques for coupling light from a waveguide array to a single mode fiber array are described. In an embodiment, lateral misalignment of an array of focusing lenses and an array of optical fiber ferrules held into alignment by a lens holder sub-assembly is compensated by tilting the lens holder sub-assembly with respect to the propagation axis of the light being coupled by the lens holder-subassembly. Since the amount of tilt can be adjusted according to the degree of lateral misalignment, lens holder sub-assemblies manufactured with varying degrees of misalignment may be utilized to couple light into single mode fiber-optic cable. In addition, the same technique can also be used to compensate for other defects as well, such as angular errors in manufacturing or placement of a turning mirror or prism used to direct light into the lens holder sub-assembly.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: January 31, 2017
    Assignee: Cisco Technology, Inc.
    Inventors: Ravinder Kachru, Chris Togami, Kishor Desai
  • Patent number: 9508687
    Abstract: A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: November 29, 2016
    Assignee: Tessera, Inc.
    Inventors: Kishor Desai, Qwai H. Low, Chok J. Chia, Charles G. Woychik, Huailiang Wei
  • Patent number: 9435965
    Abstract: An apparatus for providing single mode optical signal coupling between an opto-electronic transceiver and a single mode optical fiber array takes the form of a lens array and a ferrule component. The lens array includes a plurality of separate lens element disposed to intercept a like plurality of single mode optical output signal from the opto-electronic transceiver and provide as an output a focused version thereof. The ferrule component includes a plurality of single mode fiber stubs that are passively aligned with the lens array and support the transmission of the focused, single mode optical output signals towards the associated single mode optical fiber array.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: September 6, 2016
    Assignee: Cisco Technology, Inc.
    Inventors: Chris Kiyoshi Togami, Soham Pathak, Kalpendu Shastri, Bipin Dama, Vipulkumar Patel, Ravinder Kachru, Kishor Desai
  • Patent number: 9433100
    Abstract: A component can include a substrate having a first surface and a second surface remote therefrom, an opening extending in a direction between the first and second surfaces, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The conductive via can include a plurality of base particles each including a first region of a first metal substantially covered by a layer of a second metal different from the first metal. The base particles can be metallurgically joined together and the second metal layers of the particles can be at least partially diffused into the first regions. The conductive via can include voids interspersed between the joined base particles. The voids can occupy 10% or more of a volume of the conductive via.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: August 30, 2016
    Assignee: Tessera, Inc.
    Inventors: Charles G. Woychik, Kishor Desai, Ilyas Mohammed, Terrence Caskey
  • Patent number: 9417412
    Abstract: An arrangement for providing passive alignment of optical components on a common substrate uses a set of reference cavities, where each optical device is positioned within a separate reference cavity. The reference cavities are formed to have a predetermined depth, with perimeters slightly larger than the footprint of their associated optical components. The reference cavity includes at least one right-angle corner that is used as a registration corner against which a right-angle corner of an associated optical component is positioned. The placement of each optical component in its own reference cavity allows for passive optical alignment to be achieved by placing each component against its predefined registration corner.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: August 16, 2016
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Kalpendu Shastri, Ravinder Kachru, Kishor Desai
  • Patent number: 9401288
    Abstract: An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent a first surface and a second end adjacent a second surface. A second support portion has a plurality of second conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent the first surface and a second end adjacent the second surface. A redistribution layer is disposed between the second surfaces of the first and second support portions, electrically connecting at least some of the first vias with at least some of the second vias. The first and second support portions can have a coefficient of thermal expansion (“CTE”) of less than 12 parts per million per degree, Celsius (“ppm/° C.”).
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: July 26, 2016
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Kishor Desai
  • Publication number: 20160209606
    Abstract: An arrangement for providing passive alignment of optical components on a common substrate uses a set of reference cavities, where each optical device is positioned within a separate reference cavity. The reference cavities are formed to have a predetermined depth, with perimeters slightly larger than the footprint of their associated optical components. The reference cavity includes at least one right-angle corner that is used as a registration corner against which a right-angle corner of an associated optical component is positioned. The placement of each optical component in its own reference cavity allows for passive optical alignment to be achieved by placing each component against its predefined registration corner.
    Type: Application
    Filed: July 24, 2014
    Publication date: July 21, 2016
    Inventors: Kalpendu SHASTRI, Ravinder KACHRU, Kishor DESAI
  • Publication number: 20160161684
    Abstract: Techniques for coupling light from a waveguide array to a single mode fiber array are described. In an embodiment, lateral misalignment of an array of focusing lenses and an array of optical fiber ferrules held into alignment by a lens holder sub-assembly is compensated by tilting the lens holder sub-assembly with respect to the propagation axis of the light being coupled by the lens holder-subassembly. Since the amount of tilt can be adjusted according to the degree of lateral misalignment, lens holder sub-assemblies manufactured with varying degrees of misalignment may be utilized to couple light into single mode fiber-optic cable. In addition, the same technique can also be used to compensate for other defects as well, such as angular errors in manufacturing or placement of a turning mirror or prism used to direct light into the lens holder sub-assembly.
    Type: Application
    Filed: February 17, 2016
    Publication date: June 9, 2016
    Inventors: Ravinder KACHRU, Chris TOGAMI, Kishor DESAI
  • Patent number: 9343450
    Abstract: A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: May 17, 2016
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Kalpendu Shastri, Vipulkumar Patel, Mark Webster, Prakash Gothoskar, Ravinder Kachru, Soham Pathak, Rao V. Yelamarty, Thomas Daugherty, Bipin Dama, Kaushik Patel, Kishor Desai
  • Publication number: 20160075640
    Abstract: The present invention relates to a novel process for preparation of 2-Cyano-3,3-diarylacrylates by the Knoevenagel condensation of Cyanoacetic esters and Arylketones using ammonium compound and acetic acid and without the use of organic solvent.
    Type: Application
    Filed: December 6, 2013
    Publication date: March 17, 2016
    Inventors: Bharat Bhikaji PARAB, Rushit Ramakant MHATRE, Anchita Ravinder TANWAR, Archana Kishor DESAI
  • Patent number: 9274290
    Abstract: Techniques for coupling light from a waveguide array to a single mode fiber array are described. In an embodiment, lateral misalignment of an array of focusing lenses and an array of optical fiber ferrules held into alignment by a lens holder sub-assembly is compensated by tilting the lens holder sub-assembly with respect to the propagation axis of the light being coupled by the lens holder-subassembly. Since the amount of tilt can be adjusted according to the degree of lateral misalignment, lens holder sub-assemblies manufactured with varying degrees of misalignment may be utilized to couple light into single mode fiber-optic cable. In addition, the same technique can also be used to compensate for other defects as well, such as angular errors in manufacturing or placement of a turning mirror or prism used to direct light into the lens holder sub-assembly.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: March 1, 2016
    Assignee: Cisco Technology, Inc.
    Inventors: Ravinder Kachru, Chris Togami, Kishor Desai
  • Patent number: 9235019
    Abstract: An apparatus for providing self-aligned optical coupling between an opto-electronic substrate and a fiber array, where the substrate is enclosed by a transparent lid such that the associated optical signals enter and exit the arrangement through the transparent lid. The apparatus takes the form of a two-part connectorized fiber array assembly where the two pieces uniquely mate to form a self-aligned configuration. A first part, in the form of a plate, is attached to the transparent lid in the area where the optical signals pass through. The first plate includes a central opening with inwardly-tapering sidewalls surrounding its periphery. A second plate is also formed to include a central opening and has a lower protrusion with inwardly-tapering sidewalls that mate with the inwardly-tapering sidewalls of the first plate to form the self-aligned connectorized fiber array assembly. The fiber array is then attached to the second plate in a self-aligned fashion.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: January 12, 2016
    Assignee: Cisco Technology, Inc.
    Inventors: Kalpendu Shastri, Soham Pathak, Utpal Chakrabarti, Vipulkumar Patel, Bipin Dama, Ravinder Kachru, Kishor Desai