Abstract: A configurable logic gate array having an array of logic gates adapted for selective electrical interconnection to provide a predetermined logic function on a plurality of input logic signals fed to the configured gate array and produce such predetermined logic function as an output signal at an array output terminal. An output buffer circuit is coupled between the output of an interconnected gate and the array output terminal. A parametric testing circuit is responsive to a control signal for electrically coupling, during a normal operating mode, the output of the interconnected gate to the array output terminal, or, during a parameter testing mode, a logic signal source for producing "high" and "low" logic output voltages representative of the logic output voltage produced by the logic gates in response to the logic input signals.