Patents by Inventor Kishor Pathak
Kishor Pathak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11928535Abstract: Systems and methods for using QR codes to track, monitor, and consolidate transactions are disclosed. In one embodiment, a system may receive a request from a first device to generate a first QR code associated with a first account. The system may generate the first QR code and send the first QR code to the first device. The system may receive a request from the first device to share a QR code with a second device. The system may update associated data to indicate a sharing of a QR code with the second device. The system may generate a second QR code associated with a second account of the second device and linked to the first account, so that use of the second QR code can be tracked and monitored. The system may send the second QR code to the second device.Type: GrantFiled: January 23, 2023Date of Patent: March 12, 2024Assignee: PayPal, Inc.Inventors: Sunil Kishor Pathak, Venkatesan Dasarathan, Sreevarshini Kuppuraj
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Publication number: 20230274116Abstract: Systems and methods for using QR codes to track, monitor, and consolidate transactions are disclosed. In one embodiment, a system may receive a request from a first device to generate a first QR code associated with a first account. The system may generate the first QR code and send the first QR code to the first device. The system may receive a request from the first device to share a QR code with a second device. The system may update associated data to indicate a sharing of a QR code with the second device. The system may generate a second QR code associated with a second account of the second device and linked to the first account, so that use of the second QR code can be tracked and monitored. The system may send the second QR code to the second device.Type: ApplicationFiled: January 23, 2023Publication date: August 31, 2023Inventors: Sunil Kishor Pathak, Venkatesan Dasarathan, Sreevarshini Kuppuraj
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Publication number: 20230034841Abstract: Systems and methods for using QR codes to track, monitor, and consolidate transactions are disclosed. In one embodiment, a system may receive a request from a first device to generate a first QR code associated with a first account. The system may generate the first QR code and send the first QR code to the first device. The system may receive a request from the first device to share a QR code with a second device. The system may update associated data to indicate a sharing of a QR code with the second device. The system may generate a second QR code associated with a second account of the second device and linked to the first account, so that use of the second QR code can be tracked and monitored. The system may send the second QR code to the second device.Type: ApplicationFiled: July 27, 2021Publication date: February 2, 2023Inventors: Sunil Kishor Pathak, Venkatesan Dasarathan, Sreevarshini Kuppuraj
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Patent number: 11562191Abstract: Systems and methods for using QR codes to track, monitor, and consolidate transactions are disclosed. In one embodiment, a system may receive a request from a first device to generate a first QR code associated with a first account. The system may generate the first QR code and send the first QR code to the first device. The system may receive a request from the first device to share a QR code with a second device. The system may update associated data to indicate a sharing of a QR code with the second device. The system may generate a second QR code associated with a second account of the second device and linked to the first account, so that use of the second QR code can be tracked and monitored. The system may send the second QR code to the second device.Type: GrantFiled: July 27, 2021Date of Patent: January 24, 2023Assignee: PayPal, Inc.Inventors: Sunil Kishor Pathak, Venkatesan Dasarathan, Sreevarshini Kuppuraj
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Patent number: 11551120Abstract: The present disclosure relates to system and methods for predicting performance caused by software code changes. For this purpose, an augmented machine learning model predicts a latency of software module with updated code executed in a production environment. In some aspects, the latency is predicted based on a change of deviation that is determined by comparing the latency of the software module with updated code and the latency of the software module without updated code, whereas the software modules are executed in environments different from the production environment.Type: GrantFiled: June 29, 2020Date of Patent: January 10, 2023Assignee: PayPal, Inc.Inventors: Sunil Kishor Pathak, Prasanth Kuricheti, Srikanth Yadavilli
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Publication number: 20210406721Abstract: The present disclosure relates to system and methods for predicting performance caused by software code changes. For this purpose, an augmented machine learning model predicts a latency of software module with updated code executed in a production environment. In some aspects, the latency is predicted based on a change of deviation that is determined by comparing the latency of the software module with updated code and the latency of the software module without updated code, whereas the software modules are executed in environments different from the production environment.Type: ApplicationFiled: June 29, 2020Publication date: December 30, 2021Inventors: Sunil Kishor Pathak, Prasanth Kuricheti, Srikanth Yadavilli
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Patent number: 9298744Abstract: A computer implemented method and apparatus for ordering images in an image set based on social interactions and viewer preferences. The method comprises ordering the images in an image set based on social interactions with the image set and viewer preferences; and providing for display, the ordered images.Type: GrantFiled: March 31, 2014Date of Patent: March 29, 2016Assignee: ADOBE SYSTEMS INCORPORATEDInventors: Sunil Kishor Pathak, Vipul Jain
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Patent number: 9234162Abstract: Embodiments of the disclosure are directed to a stable cleaning composition comprising: a chelating agent, a low-foaming, temperature- and alkaline-stable surfactant, and water. Other embodiments relate to the methods of preparing the stable cleaning compositions and the methods of their use. The stable cleaning composition described here is a low cost cleaning composition for use either alone or as an additive to a cleaning agent.Type: GrantFiled: January 25, 2013Date of Patent: January 12, 2016Assignee: LMC ENTERPRISESInventors: Kishor Pathak, Marija Rajovic-Simovic
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Publication number: 20150278251Abstract: A computer implemented method and apparatus for ordering images in an image set based on social interactions and viewer preferences. The method comprises ordering the images in an image set based on social interactions with the image set and viewer preferences; and providing for display, the ordered images.Type: ApplicationFiled: March 31, 2014Publication date: October 1, 2015Applicant: Adobe Systems IncorporatedInventors: Sunil Kishor Pathak, Vipul Jain
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Publication number: 20140298281Abstract: System-on-chip (SoC) designs include large amounts of interconnected intellectual property blocks and standard-cell logic using complex bus fabrics. Today SoC design-closure that validates design targets of area, timing, congestion and power constraints is accomplished post routing as over 80% of validation problems are due to global-interconnect. A method is disclosed that allows the designers to achieve global design-closure and physical topology constraints, early in the design cycle, at much higher levels of abstraction. In particular, logic hierarchy of the design is converted into a physical hierarchy of functional-related clusters of locally-connected logic. The clusters and inter-cluster global connections can be refined to meet design constraints in order to generate a top-level floor-plan in the form of library and constraint files.Type: ApplicationFiled: October 16, 2013Publication date: October 2, 2014Applicant: Atrenta, Inc.Inventors: Ravi Varadarajan, Jitendra Gupta, Sanjiv Mathur, Priyank Mittal, Kaushal Kishore Pathak, Kshitiz Krishna, Anup Nagrath, Ritesh Mittal
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Patent number: 8839171Abstract: System-on-chip (SoC) designs include large amounts of interconnected intellectual property blocks and standard-cell logic using complex bus fabrics. Today SoC design-closure that validates design targets of area, timing, congestion and power constraints is accomplished post routing as over 80% of validation problems are due to global-interconnect. A method is disclosed that allows the designers to achieve global design-closure and physical topology constraints, early in the design cycle, at much higher levels of abstraction. In particular, logic hierarchy of the design is converted into a physical hierarchy of functional-related clusters of locally-connected logic. The clusters and inter-cluster global connections can be refined to meet design constraints in order to generate a top-level floor-plan in the form of library and constraint files.Type: GrantFiled: October 16, 2013Date of Patent: September 16, 2014Assignee: Atrenta, Inc.Inventors: Ravi Varadarajan, Jitendra Gupta, Sanjiv Mathur, Priyank Mittal, Kaushal Kishore Pathak, Kshitiz Krishna, Anup Nagrath, Ritesh Mittal
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Publication number: 20140209127Abstract: Embodiments of the disclosure are directed to a stable cleaning composition comprising: a chelating agent, a low-foaming, temperature- and alkaline-stable surfactant, and water. Other embodiments relate to the methods of preparing the stable cleaning compositions and the methods of their use. The stable cleaning composition described here is a low cost cleaning composition for use either alone or as an additive to a cleaning agent.Type: ApplicationFiled: January 25, 2013Publication date: July 31, 2014Applicant: LMC ENTERPRISESInventors: KISHOR PATHAK, MARIJA RAJOVIC-SIMOVIC
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Patent number: 8732647Abstract: An electronic design automation method implemented in a computing system is provided for creating a physical connections netlist for a pre-floorplan partitioned design file of 3D integrated circuits. The inputs are a 3D stack defining the topology of multiple dies, and a given design partitioning. The design partitioning defines the logic implemented in each die. The method identifies through-silicon-vias (TSVs), bump pins (BPs) and net connections.Type: GrantFiled: August 28, 2013Date of Patent: May 20, 2014Assignee: Atrenta, Inc.Inventors: Lenuta Georgeta Claudia Rusu, Kaushal Kishore Pathak, Ravi Varadarajan
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Patent number: 6617298Abstract: A composition for the removal of grease and oil spots from concrete, asphalt surfaces, etc., comprises a degreaser and a diatomaceous earth. The degreaser comprises a number of ingredients of respective percentage ranges to emulsify the grease or oil which is then absorbed by the diatomaceous earth.Type: GrantFiled: December 31, 2002Date of Patent: September 9, 2003Inventors: Dennis S. Morrow, William T. Morrow, Kishor Pathak