Patents by Inventor Kishor V. Desai
Kishor V. Desai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10678005Abstract: Two semiconductor chips are optically aligned to form a hybrid semiconductor device. Both chips have optical waveguides and alignment surface positioned at precisely-defined complementary vertical offsets from optical axes of the corresponding waveguides, so that the waveguides are vertically aligned when one of the chips is placed atop the other with their alignment surface abutting each other. The position of the at least one of the alignment surface in a layer stack of its chip is precisely defined by epitaxy. The chips are bonded at offset bonding pads with the alignment surfaces abutting in the absence of bonding material therebetween.Type: GrantFiled: January 16, 2019Date of Patent: June 9, 2020Assignee: Elenion Technologies, LLCInventors: David Henry Kinghorn, Ari Jason Novack, Holger N. Klein, Nathan A. Nuttall, Kishor V. Desai, Daniel J. Blumenthal, Michael J. Hochberg, Ruizhi Shi
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Publication number: 20190179091Abstract: Two semiconductor chips are optically aligned to form a hybrid semiconductor device. Both chips have optical waveguides and alignment surface positioned at precisely-defined complementary vertical offsets from optical axes of the corresponding waveguides, so that the waveguides are vertically aligned when one of the chips is placed atop the other with their alignment surface abutting each other. The position of the at least one of the alignment surface in a layer stack of its chip is precisely defined by epitaxy. The chips are bonded at offset bonding pads with the alignment surfaces abutting in the absence of bonding material therebetween.Type: ApplicationFiled: January 16, 2019Publication date: June 13, 2019Inventors: David Henry Kinghorn, Ari Jason Novack, Holger N. Klein, Nathan A. Nuttall, Kishor V. Desai, Daniel J. Blumenthal, Michael J. Hochberg, Ruizhi Shi
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Patent number: 10222565Abstract: Two semiconductor chips are optically aligned to form a hybrid semiconductor device. Both chips have optical waveguides and alignment surface positioned at precisely-defined complementary vertical offsets from optical axes of the corresponding waveguides, so that the waveguides are vertically aligned when one of the chips is placed atop the other with their alignment surface abutting each other. The position of the at least one of the alignment surface in a layer stack of its chip is precisely defined by epitaxy. The chips are bonded at offset bonding pads with the alignment surfaces abutting in the absence of bonding material therebetween.Type: GrantFiled: October 13, 2017Date of Patent: March 5, 2019Assignee: Elenion Technologies, LLCInventors: David Henry Kinghorn, Ari Jason Novack, Holger N. Klein, Nathan A. Nuttall, Kishor V. Desai, Daniel J. Blumenthal, Michael J. Hochberg, Ruizhi Shi
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Publication number: 20180052290Abstract: Two semiconductor chips are optically aligned to form a hybrid semiconductor device. Both chips have optical waveguides and alignment surface positioned at precisely-defined complementary vertical offsets from optical axes of the corresponding waveguides, so that the waveguides are vertically aligned when one of the chips is placed atop the other with their alignment surface abutting each other. The position of the at least one of the alignment surface in a layer stack of its chip is precisely defined by epitaxy. The chips are bonded at offset bonding pads with the alignment surfaces abutting in the absence of bonding material therebetween.Type: ApplicationFiled: October 13, 2017Publication date: February 22, 2018Inventors: David Henry Kinghorn, Ari Jason Novack, Holger N. Klein, Nathan A. Nuttall, Kishor V. Desai, Daniel J. Blumenthal, Michael J. Hochberg, Ruizhi Shi
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Patent number: 9817197Abstract: Two semiconductor chips are optically aligned to form a hybrid semiconductor device. Both chips have optical waveguides and alignment surface positioned at precisely-defined complementary vertical offsets from optical axes of the corresponding waveguides, so that the waveguides are vertically aligned when one of the chips is placed atop the other with their alignment surface abutting each other. The position of the at least one of the alignment surface in a layer stack of its chip is precisely defined by epitaxy. The chips are bonded at offset bonding pads with the alignment surfaces abutting in the absence of bonding material therebetween.Type: GrantFiled: March 31, 2016Date of Patent: November 14, 2017Assignee: Elenion Technologies, LLCInventors: David Henry Kinghorn, Ari Jason Novack, Holger N. Klein, Nathan A. Nuttall, Kishor V. Desai, Daniel J. Blumenthal, Michael J. Hochberg, Ruizhi Shi
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Publication number: 20160291265Abstract: Two semiconductor chips are optically aligned to form a hybrid semiconductor device. Both chips have optical waveguides and alignment surface positioned at precisely-defined complementary vertical offsets from optical axes of the corresponding waveguides, so that the waveguides are vertically aligned when one of the chips is placed atop the other with their alignment surface abutting each other. The position of the at least one of the alignment surface in a layer stack of its chip is precisely defined by epitaxy. The chips are bonded at offset bonding pads with the alignment surfaces abutting in the absence of bonding material therebetween.Type: ApplicationFiled: March 31, 2016Publication date: October 6, 2016Inventors: David Henry Kinghorn, Ari Jason Novack, Holger N. Klein, Nathan A. Nuttall, Kishor V. Desai, Daniel J. Blumenthal, Michael J. Hochberg, Ruizhi Shi
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Patent number: 9349669Abstract: A microelectronic component with circuitry includes a substrate (possibly semiconductor) having an opening in a top surface. The circuitry includes a conductive via (possibly metal) in the opening. The opening has a first sidewall of a first material, and the conductive via has a second sidewall of a second material (possibly metal). At least at one side of the opening, the first and second sidewalls are spaced from each other at the top surface of the substrate but the first and second sidewalls meet below the top surface of the substrate at a meeting location. Between the meeting location and the top surface of the substrate, the first and second sidewalls are separated by a third material (possibly foam) which is a dielectric different from the first material. The third material lowers thermal stress in case of thermal expansion compared to a structure in which the third material were replaced with the second material.Type: GrantFiled: March 10, 2015Date of Patent: May 24, 2016Assignee: Invensas CorporationInventors: Cyprian Emeka Uzoh, Charles G. Woychik, Terrence Caskey, Kishor V. Desai, Huailiang Wei, Craig Mitchell, Belgacem Haba
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Patent number: 9151950Abstract: Techniques and configurations are provided for packaging optoelectronic devices. In particular, a lid component of an optoelectronic device is provided, and the lid component is configured to cover active components of the optoelectronic device. An optically transparent wall is also provided. The optically transparent wall is coated with an anti-reflective material and configured to interface with a section of the lid component. The optically transparent wall is joined with the section of the lid component such that the optically transparent wall and the lid provide a seal for the active components of the optoelectronic device. Additionally, the lid component has a top surface and a plurality of side surfaces that are coupled to the top surface. An optically transparent wall coated with an anti-reflective material adhesively joins to the top surface and one or more side surfaces.Type: GrantFiled: November 16, 2012Date of Patent: October 6, 2015Assignee: Cisco Technology, Inc.Inventors: Kishor V. Desai, Ravinder Kachru, Soham R. Pathak, Utpal Kumar Chakrabarti
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Publication number: 20150187673Abstract: A microelectronic component with circuitry includes a substrate (possibly semiconductor) having an opening in a top surface. The circuitry includes a conductive via (possibly metal) in the opening. The opening has a first sidewall of a first material, and the conductive via has a second sidewall of a second material (possibly metal). At least at one side of the opening, the first and second sidewalls are spaced from each other at the top surface of the substrate but the first and second sidewalls meet below the top surface of the substrate at a meeting location. Between the meeting location and the top surface of the substrate, the first and second sidewalls are separated by a third material (possibly foam) which is a dielectric different from the first material. The third material lowers thermal stress in case of thermal expansion compared to a structure in which the third material were replaced with the second material.Type: ApplicationFiled: March 10, 2015Publication date: July 2, 2015Inventors: Cyprian Emeka Uzoh, Charles G. Woychik, Terrence Caskey, Kishor V. Desai, Huailiang Wei, Craig Mitchell, Belgacem Haba
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Patent number: 9000600Abstract: A component can include a substrate and a conductive via extending within an opening in the substrate. The substrate can have first and second opposing surfaces. The opening can extend from the first surface towards the second surface and can have an inner wall extending away from the first surface. A dielectric material can be exposed at the inner wall. The conductive via can define a relief channel within the opening adjacent the first surface. The relief channel can have an edge within a first distance from the inner wall in a direction of a plane parallel to and within five microns below the first surface, the first distance being the lesser of one micron and five percent of a maximum width of the opening in the plane. The edge can extend along the inner wall to span at least five percent of a circumference of the inner wall.Type: GrantFiled: March 11, 2014Date of Patent: April 7, 2015Assignee: Invensas CorporationInventors: Cyprian Emeka Uzoh, Charles G. Woychik, Terrence Caskey, Kishor V. Desai, Huailiang Wei, Craig Mitchell, Belgacem Haba
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Publication number: 20140217607Abstract: A component can include a substrate and a conductive via extending within an opening in the substrate. The substrate can have first and second opposing surfaces. The opening can extend from the first surface towards the second surface and can have an inner wall extending away from the first surface. A dielectric material can be exposed at the inner wall. The conductive via can define a relief channel within the opening adjacent the first surface. The relief channel can have an edge within a first distance from the inner wall in a direction of a plane parallel to and within five microns below the first surface, the first distance being the lesser of one micron and five percent of a maximum width of the opening in the plane. The edge can extend along the inner wall to span at least five percent of a circumference of the inner wall.Type: ApplicationFiled: March 11, 2014Publication date: August 7, 2014Applicant: Invensas CorporationInventors: Cyprian Emeka Uzoh, Charles G. Woychik, Terrence Caskey, Kishor V. Desai, Huailiang Wei, Craig Mitchell, Belgacem Haba
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Patent number: 8772946Abstract: A component can include a substrate and a conductive via extending within an opening in the substrate. The substrate can have first and second opposing surfaces. The opening can extend from the first surface towards the second surface and can have an inner wall extending away from the first surface. A dielectric material can be exposed at the inner wall. The conductive via can define a relief channel within the opening adjacent the first surface. The relief channel can have an edge within a first distance from the inner wall in a direction of a plane parallel to and within five microns below the first surface, the first distance being the lesser of one micron and five percent of a maximum width of the opening in the plane. The edge can extend along the inner wall to span at least five percent of a circumference of the inner wall.Type: GrantFiled: June 8, 2012Date of Patent: July 8, 2014Assignee: Invensas CorporationInventors: Cyprian Emeka Uzoh, Charles G. Woychik, Terrence Caskey, Kishor V. Desai, Huailiang Wei, Craig Mitchell, Belgacem Haba
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Publication number: 20140043685Abstract: Techniques and configurations are provided for packaging optoelectronic devices. In particular, a lid component of an optoelectronic device is provided, and the lid component is configured to cover active components of the optoelectronic device. An optically transparent wall is also provided. The optically transparent wall is coated with an anti-reflective material and configured to interface with a section of the lid component. The optically transparent wall is joined with the section of the lid component such that the optically transparent wall and the lid provide a seal for the active components of the optoelectronic device. Additionally, the lid component has a top surface and a plurality of side surfaces that are coupled to the top surface. An optically transparent wall coated with an anti-reflective material adhesively joins to the top surface and one or more side surfaces.Type: ApplicationFiled: November 16, 2012Publication date: February 13, 2014Applicant: CISCO TECHNOLOGY, INC.Inventors: Kishor V. Desai, Ravinder Kachru, Soham R. Pathak, Utpal Kumar Chakrabarti
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Publication number: 20130328186Abstract: A component can include a substrate and a conductive via extending within an opening in the substrate. The substrate can have first and second opposing surfaces. The opening can extend from the first surface towards the second surface and can have an inner wall extending away from the first surface. A dielectric material can be exposed at the inner wall. The conductive via can define a relief channel within the opening adjacent the first surface. The relief channel can have an edge within a first distance from the inner wall in a direction of a plane parallel to and within five microns below the first surface, the first distance being the lesser of one micron and five percent of a maximum width of the opening in the plane. The edge can extend along the inner wall to span at least five percent of a circumference of the inner wall.Type: ApplicationFiled: June 8, 2012Publication date: December 12, 2013Applicant: INVENSAS CORPORATIONInventors: Cyprian Emeka Uzoh, Charles G. Woychik, Terrence Caskey, Kishor V. Desai, Huailiang Wei, Craig Mitchell, Belgacem Haba
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Patent number: 8580621Abstract: A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A copper-containing layer is formed on the nickel-containing layer prior to subjecting the electronic device to a reflow process.Type: GrantFiled: January 29, 2013Date of Patent: November 12, 2013Assignee: LSI CorporationInventors: Mark A. Bachman, John W. Osenbach, Kishor V. Desai
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Patent number: 8378485Abstract: A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A copper-containing layer is formed on the nickel-containing layer prior to subjecting the electronic device to a reflow process.Type: GrantFiled: July 13, 2009Date of Patent: February 19, 2013Assignee: LSI CorporationInventors: Mark A. Bachman, John W. Osenbach, Kishor V. Desai
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Publication number: 20110006415Abstract: A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A copper-containing layer is formed on the nickel-containing layer prior to subjecting the electronic device to a reflow process.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Applicant: LSI CorporationInventors: Mark A. Bachman, John W. Osenbach, Kishor V. Desai
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Patent number: 7727781Abstract: Typical testing of solder joints, (e.g. joints at printed circuit board pads) has not proven totally predictive of the ultimate performance of such joints. It has been found that this lack of reliability is, at least in part, due to the tendency during testing for these pads to lose adhesion to, or delaminate from, the underlying substrate. In contrast, such occurrence is not typical of phenomena induced during typical device usage. To remove this source of unreliability, a test structure is made together with the manufacturing device lot. The same pad processing is used and the pad size is substantially enlarged in the test structure. The test structure is employed to predict performance of devices in the lot and then the lot is processed accordingly.Type: GrantFiled: July 22, 2008Date of Patent: June 1, 2010Assignee: Agere Systems Inc.Inventors: Joze Eura Antol, Kishor V. Desai, John William Osenbach, Brian Thomas Vaccaro
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Publication number: 20100022034Abstract: Typical testing of solder joints, (e.g. joints at printed circuit board pads) has not proven totally predictive of the ultimate performance of such joints. It has been found that this lack of reliability is, at least in part, due to the tendency during testing for these pads to lose adhesion to, or delaminate from, the underlying substrate. In contrast, such occurrence is not typical of phenomena induced during typical device usage. To remove this source of unreliability, a test structure is made together with the manufacturing device lot. The same pad processing is used and the pad size is substantially enlarged in the test structure. The test structure is employed to predict performance of devices in the lot and then the lot is processed accordingly.Type: ApplicationFiled: July 22, 2008Publication date: January 28, 2010Inventors: Joze Eura Antol, Kishor V. Desai, John William Osenbach, Brian Thomas Vaccaro
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Patent number: 7119432Abstract: A semiconductor package comprising a packaging substrate, a semiconductor die mounted with the substrate, a heatspreader, and a multi-layer heat transfer element arranged between the semiconductor die and the heat spreader to enable thermal communication between the die and the heat spreader is disclosed. The multi-layer heat transfer element includes a core spacer element sandwiched between a first layer of thermally conductive reflowable material and a second layer of thermally conductive reflowable material. Also disclosed are methods for forming such semiconductor packages and for forming multilayer heat transfer elements.Type: GrantFiled: April 7, 2004Date of Patent: October 10, 2006Assignee: LSI Logic CorporationInventors: Kishor V. Desai, Maniam B. Alagaratnam