Patents by Inventor Kishore K. Muchherla

Kishore K. Muchherla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230230645
    Abstract: A method includes determining that a ratio of valid data portions to a total quantity of data portions of a block of memory cells is greater than or less than a valid data portion threshold and determining that health characteristics for the valid data portions of the block of memory cells are greater than or less than a valid data health characteristic threshold. The method further includes performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is greater than the valid data portion threshold and performing a second media management operation on at least a portion of the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is less than the valid data portion threshold and the health characteristics for the valid data portions are greater than the valid data health characteristic threshold.
    Type: Application
    Filed: March 23, 2023
    Publication date: July 20, 2023
    Inventors: Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore K. Muchherla
  • Patent number: 11694763
    Abstract: A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: July 4, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Niccolo' Righetti, Jeffrey S. McNeil, Jr., Akira Goda, Todd A. Marquart, Mark A. Helm, Gil Golov, Jeremy Binfet, Carmine Miccoli, Giuseppina Puzzilli
  • Patent number: 11688479
    Abstract: A first group of memory cells of a memory device can be subjected to a particular quantity of program/erase cycles (PECs) in response to a programming operation performed on a second group of memory cells of the memory device. Subsequent to subjecting the first group of memory cells to the particular quantity of PECs, a data retention capability of the first group of memory cells can be assessed.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: June 27, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Giuseppina Puzzilli, Karl D. Schuh, Jeffrey S. McNeil, Jr., Kishore K. Muchherla, Ashutosh Malshe, Niccolo' Righetti
  • Publication number: 20230195566
    Abstract: Methods, devices, and systems related to crossed matrix parity in a memory device are described. In an example, a first group of sets of parity data that each protect data stored in a row of memory cells of an array is generated. Further, a second group of sets of parity data that each protect data stored in a column of memory cells of an array is generated. The first set of parity data and the second set of parity data is sent to a host for further ECC processing. The host provides ECC data to the memory device based on the first set of parity data and the second set of parity data. The memory device repairs memory cellsor retires memory cells based on the provided ECC data.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 22, 2023
    Inventors: Christopher J. Bueb, Kishore K. Muchherla
  • Publication number: 20230195567
    Abstract: Methods, devices, and systems related to crossed matrix parity in a memory device are described. In an example, a first plurality of sets of parity data to memory cells in the array that each protect data stored in a row of memory cells of the array can be written to the array. Further, a second plurality of sets of parity data to memory cells in the array that each protect data stored in a column of memory cells of the array can be written to the array. The first plurality of sets of parity data and the second plurality of sets of parity data can be sent to a processor for further ECC processing. Error correction data can be received from a processor that indicates a cluster of data that includes a threshold quantity of errors. An error correction can be performed on the cluster of data.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 22, 2023
    Inventors: Christopher J. Bueb, Kishore K. Muchherla
  • Publication number: 20230168829
    Abstract: A method includes determining respective valid translation unit counts of a block of non-volatile memory cells over a period of time, determining a rate of change of the respective valid translation unit counts of the block of non-volatile memory cells over the period of time, comparing the rate of change of the valid translation unit counts to a bin transition rate, and based on comparing the rate of change of the valid translation unit counts to the bin transition rate, performing a media management operation on the block of non-volatile memory cells.
    Type: Application
    Filed: January 31, 2023
    Publication date: June 1, 2023
    Inventors: Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore K. Muchherla
  • Patent number: 11663104
    Abstract: A method includes writing received data sequentially to a particular location of a cyclic buffer of a memory device according to a first set of threshold voltage distributions. The method further includes performing a touch up operation on the particular location by adjusting the first set of threshold voltage distributions of the data to a second set of threshold voltage distributions in response to a determination that a trigger event has occurred. The second set of threshold voltage distributions can have a larger read window between adjacent threshold voltage distributions of the second set than that of the first set of threshold voltage distributions.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: May 30, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey S. McNeil, Jr., Niccolo′ Righetti, Kishore K. Muchherla, Akira Goda, Todd A. Marquart, Mark A. Helm, Gil Golov, Jeremy Binfet, Carmine Miccoli, Giuseppina Puzzilli
  • Publication number: 20230141181
    Abstract: A method includes determining a respective number of and respective locations of valid data portions of a plurality of blocks of NAND memory cells, based on the respective locations of the valid data portions, determining respective dispersions of the valid data portions within the plurality of blocks of NAND memory cells, based at least on the respective dispersions, selecting a block of NAND memory cells from the plurality of blocks of NAND memory cells, and performing a folding operation on the selected block.
    Type: Application
    Filed: January 4, 2023
    Publication date: May 11, 2023
    Inventors: Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore K. Muchherla
  • Patent number: 11615858
    Abstract: A method includes determining that a ratio of valid data portions to a total quantity of data portions of a block of memory cells is greater than or less than a valid data portion threshold and determining that health characteristics for the valid data portions of the block of memory cells are greater than or less than a valid data health characteristic threshold. The method further includes performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is greater than the valid data portion threshold and performing a second media management operation on at least a portion of the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is less than the valid data portion threshold and the health characteristics for the valid data portions are greater than the valid data health characteristic threshold.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: March 28, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore K. Muchherla
  • Publication number: 20230085178
    Abstract: A system includes a memory device including a plurality of groups of memory cells and a processing device that is operatively coupled to the memory device. The processing device is to receive a request to determine a reliability of the plurality of groups of memory cells. The processing device is further to perform, in response to receipt of the request, a scan operation on a sample portion of the plurality of groups of memory cells to determine a reliability of the sample portion that is representative of the reliability of the plurality of groups of memory cells.
    Type: Application
    Filed: November 22, 2022
    Publication date: March 16, 2023
    Inventors: Vamsi Pavan Rayaprolu, Karl D. Schuh, Jeffrey S. McNeil Jr., Kishore K. Muchherla, Ashutosh Malshe, Jiangang Wu
  • Patent number: 11599286
    Abstract: A method includes determining respective valid translation unit counts of a block of non-volatile memory cells over a period of time, determining a rate of change of the respective valid translation unit counts of the block of non-volatile memory cells over the period of time, comparing the rate of change of the valid translation unit counts to a bin transition rate, and based on comparing the rate of change of the valid translation unit counts to the bin transition rate, performing a media management operation on the block of non-volatile memory cells.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: March 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore K. Muchherla
  • Publication number: 20230061800
    Abstract: A method includes forming at least a portion of a first superblock using a first subset of blocks from at least one memory die of a memory sub-system and forming at least a portion of a second superblock using a second subset of blocks from the at least one memory die of the memory sub-system.
    Type: Application
    Filed: September 1, 2021
    Publication date: March 2, 2023
    Inventors: Kishore K. Muchherla, Jianmin Huang, Xiangang Luo
  • Publication number: 20230057863
    Abstract: A method includes determining that a ratio of valid data portions of a block of memory cells is greater than or less than a valid data portion threshold and performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions is greater than the valid data portion threshold. The method further includes performing a second media management operation on the block of memory cells in response to determining that the ratio of valid data portions is less than the valid data portion threshold.
    Type: Application
    Filed: November 7, 2022
    Publication date: February 23, 2023
    Inventors: Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore K. Muchherla
  • Patent number: 11586357
    Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: February 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Ashutosh Malshe, Preston A. Thomson, Michael G. Miller, Sampath K. Ratnam, Renato C. Padilla, Peter Feeley
  • Publication number: 20230044883
    Abstract: A memory component comprises a cyclic buffer partition portion and a snapshot partition portion. In response to receiving a signal that a trigger event has occurred, a processing device included in the memory component performs an error correction operation on a portion of data stored in the cyclic buffer partition portion, copies the data stored in the cyclic buffer partition portion to the snapshot partition portion in response to the error correction operation being successful, and sends the data stored in the cyclic buffer partition portion to a processing device operatively coupled to the memory component in response to the error correction operation not being successful.
    Type: Application
    Filed: October 21, 2022
    Publication date: February 9, 2023
    Inventors: Kishore K. Muchherla, Niccolo' Righetti, Jeffrey S. McNeil, JR., Akira Goda, Todd A. Marquart, Mark A. Helm, Gil Golov, Jeremy Binfet, Carmine Miccoli, Giuseppina Puzzilli
  • Patent number: 11567665
    Abstract: A method includes determining a respective number of and respective locations of valid data portions of a plurality of blocks of NAND memory cells, based on the respective locations of the valid data portions, determining respective dispersions of the valid data portions within the plurality of blocks of NAND memory cells, based at least on the respective dispersions, selecting a block of NAND memory cells from the plurality of blocks of NAND memory cells, and performing a folding operation on the selected block.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: January 31, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore K. Muchherla
  • Patent number: 11556267
    Abstract: A method includes performing a copyback operation comprising transferring, using an internal processing device, user data and header data corresponding to the user data from a first block of memory in a memory device to a register in the memory device, decoupling the user data from the header data, performing an error correction code (ECC) operation on updated header data using an external processing device, transferring, via the external processing device, the updated header data to the register, and transferring the user data and the updated header data from the register to a second block of memory in the memory device.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: January 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Niccolo′ Righetti, Jeffrey S. McNeil, Jr., Akira Goda, Todd A. Marquart, Mark A. Helm, Gil Golov, Jeremy Binfet, Carmine Miccoli, Giuseppina Puzzilli
  • Patent number: 11527294
    Abstract: A system includes a memory device including a plurality of groups of memory cells and a processing device that is operatively coupled to the memory device. The processing device is to receive a request to determine a reliability of the plurality of groups of memory cells. The processing device is further to perform, in response to receipt of the request, a scan operation on a sample portion of the plurality of groups of memory cells to determine a reliability of the sample portion that is representative of the reliability of the plurality of groups of memory cells.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: December 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Karl D. Schuh, Jeffrey S. McNeil, Jr., Kishore K. Muchherla, Ashutosh Malshe, Jiangang Wu
  • Publication number: 20220392558
    Abstract: A method includes determining that a ratio of valid data portions to a total quantity of data portions of a block of memory cells is greater than or less than a valid data portion threshold and determining that health characteristics for the valid data portions of the block of memory cells are greater than or less than a valid data health characteristic threshold. The method further includes performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is greater than the valid data portion threshold and performing a second media management operation on at least a portion of the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is less than the valid data portion threshold and the health characteristics for the valid data portions are greater than the valid data health characteristic threshold.
    Type: Application
    Filed: June 8, 2021
    Publication date: December 8, 2022
    Inventors: Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore K. Muchherla
  • Publication number: 20220391088
    Abstract: A method includes determining respective valid translation unit counts of a block of non-volatile memory cells over a period of time, determining a rate of change of the respective valid translation unit counts of the block of non-volatile memory cells over the period of time, comparing the rate of change of the valid translation unit counts to a bin transition rate, and based on comparing the rate of change of the valid translation unit counts to the bin transition rate, performing a media management operation on the block of non-volatile memory cells.
    Type: Application
    Filed: June 3, 2021
    Publication date: December 8, 2022
    Inventors: Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore K. Muchherla