Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.

Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.

Abstract: The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (SLC) cache and a second portion configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.

Abstract: Apparatuses and methods for temperature related error management are described. One or more apparatuses for temperature related error management can include an array of memory cells and a write temperature indicator appended to at least one predetermined number of bytes of the stored data in the array of memory cells. The apparatuses can include a controller configured to determine a numerical temperature difference between the write temperature indicator and a read temperature indicator and determine, from stored operations, an error management operation for the stored data based, at least in part, on comparison of the numerical temperature difference to a temperature difference threshold.

Abstract: The present disclosure is related to programming interruption management. An apparatus can be configured to detect an interruption during a programming operation and modify the programming operation to program a portion of the memory array to an uncorrectable state in response to detecting the interruption.

Abstract: The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (SLC) cache and a second portion configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.

Abstract: A memory device having a memory controller is configured to operate a hybrid cache including a dynamic cache including XLC blocks and a static cache including the SLC blocks. The memory controller is configured to disable at least one of the static cache or the dynamic cache. A method of operating a memory device includes partitioning a memory array into a first portion of SLC blocks and a second portion of XLC blocks, storing at least a portion of host data into the first portion of SLC blocks as a static cache; and storing at least another portion of the host data into the second portion of XLC blocks in an SLC mode as a dynamic cache responsive to a burst of host data being determined to be greater than the static cache can handle. Additional memory devices, methods, and computer systems are also described.

Abstract: The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (SLC) cache and a second portion configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.

Abstract: The present disclosure is related to a threshold voltage margin analysis. An example embodiment apparatus can include a memory and a controller coupled to the memory. The controller is configured to determine a previous power loss of a memory to be an asynchronous power loss, and identify a portion of the memory last subject to programming operations during the determined asynchronous power loss. The controller is further configured to perform a threshold voltage (Vt) margin analysis on the portion of the memory responsive to the determined asynchronous power loss.

Abstract: The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (SLC) cache and a second portion configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.

Abstract: The present disclosure includes a redundant array of independent NAND for a three dimensional memory array. A number of embodiments include a three-dimensional array of memory cells, wherein the array includes a plurality of pages of memory cells, a number of the plurality of pages include a parity portion of a redundant array of independent NAND (RAIN) stripe, and the parity portion of the RAIN stripe in each respective page comprises only a portion of that respective page.

Abstract: The present disclosure is related to a threshold voltage margin analysis. An example embodiment apparatus can include a memory and a controller coupled to the memory. The controller is configured to determine a previous power loss of a memory to be an asynchronous power loss, and identify a portion of the memory last subject to programming operations during the determined asynchronous power loss. The controller is further configured to perform a threshold voltage (Vt) margin analysis on the portion of the memory responsive to the determined asynchronous power loss.

Abstract: The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (SLC) cache and a second portion configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.

Abstract: Apparatuses, methods, and data structures that can be utilized to provide a read voltage offset are described. One or more apparatuses can include a memory device and a controller coupled to the memory device and configured to: access a data structure comprising write temperature data corresponding to a number of data segments stored in the memory device; read a particular data segment using a read voltage offset determined based on: the write temperature data from the data structure and corresponding to the particular data segment; and read temperature data corresponding to the particular data segment.

Abstract: The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (SLC) cache and a second portion configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.

Abstract: The present disclosure includes apparatuses and methods related to adjusting read voltages of charge-trapping flash memory. An example embodiment apparatus can include a memory array and a controller coupled to the memory array. The controller is configured to adjust a read voltage used to access a portion of the memory array based on a length of time since a last WRITE operation to the portion.

Abstract: Apparatuses and methods for temperature related error management are described. One or more apparatuses for temperature related error management can include an array of memory cells and a write temperature indicator appended to at least one predetermined number of bytes of the stored data in the array of memory cells. The apparatuses can include a controller configured to determine a numerical temperature difference between the write temperature indicator and a read temperature indicator and determine, from stored operations, an error management operation for the stored data based, at least in part, on comparison of the numerical temperature difference to a temperature difference threshold.

Abstract: The present disclosure is related to programming interruption management. An apparatus can be configured to detect an interruption during a programming operation and modify the programming operation to program a portion of the memory array to an uncorrectable state in response to detecting the interruption.

Abstract: The present disclosure includes apparatuses and methods related to adjusting read voltages of charge-trapping flash memory. An example embodiment apparatus can include a memory array and a controller coupled to the memory array. The controller is configured to adjust a read voltage used to access a portion of the memory array based on a length of time since a last WRITE operation to the portion.

Abstract: The present disclosure is related to a threshold voltage margin analysis. An example embodiment apparatus can include a memory and a controller coupled to the memory. The controller is configured to determine a previous power loss of a memory to be an asynchronous power loss, and identify a portion of the memory last subject to programming operations during the determined asynchronous power loss. The controller is further configured to perform a threshold voltage (Vt) margin analysis on the portion of the memory responsive to the determined asynchronous power loss.