Patents by Inventor Kishore Kasamsetty
Kishore Kasamsetty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220164305Abstract: A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.Type: ApplicationFiled: December 2, 2021Publication date: May 26, 2022Inventors: Frederick A. Ware, Kishore Kasamsetty
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Patent number: 11194749Abstract: A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.Type: GrantFiled: March 26, 2019Date of Patent: December 7, 2021Assignee: Rambus Inc.Inventors: Frederick A. Ware, Kishore Kasamsetty
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Publication number: 20190317912Abstract: A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.Type: ApplicationFiled: March 26, 2019Publication date: October 17, 2019Inventors: Frederick A. Ware, Kishore Kasamsetty
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Patent number: 10268619Abstract: A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.Type: GrantFiled: May 31, 2016Date of Patent: April 23, 2019Assignee: Rambus Inc.Inventors: Frederick A. Ware, Kishore Kasamsetty
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Publication number: 20160275033Abstract: A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.Type: ApplicationFiled: May 31, 2016Publication date: September 22, 2016Inventors: Frederick A. Ware, Kishore Kasamsetty
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Patent number: 9355021Abstract: In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requestor IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.Type: GrantFiled: June 4, 2013Date of Patent: May 31, 2016Assignee: Rambus Inc.Inventors: Frederick A. Ware, Kishore Kasamsetty
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Publication number: 20130339631Abstract: In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requestor IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.Type: ApplicationFiled: June 4, 2013Publication date: December 19, 2013Applicant: Rambus Inc.Inventors: Frederick A. Ware, Kishore Kasamsetty
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Patent number: 8510495Abstract: In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requestor IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.Type: GrantFiled: July 1, 2010Date of Patent: August 13, 2013Assignee: Rambus Inc.Inventors: Frederick A. Ware, Kishore Kasamsetty
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Patent number: 8391099Abstract: An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.Type: GrantFiled: May 9, 2011Date of Patent: March 5, 2013Assignee: Rambus Inc.Inventors: Kishore Kasamsetty, Lawrence Lai, Wayne Richardson
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Publication number: 20110238870Abstract: A memory system includes a memory controller coupled to at least one memory device via high-speed data and request links. The timing and voltage margins of the links are periodically calibrated to reduce bit error. The high-speed request links complicate calibration because commands issued over the uncalibrated request links can be erroneously interpreted by the memory device. Misinterpreted commands can disrupt the calibration procedure (e.g., a write command might be misinterpreted as a power-down command). The memory controller addresses this problem using a separate, low-speed control interface to issue a filter command that instructs the memory device to decline potentially disruptive requests when in a calibration mode.Type: ApplicationFiled: November 17, 2009Publication date: September 29, 2011Applicant: Rambus Inc.Inventors: Frederick A. Ware, Wayne Richardson, Kishore Kasamsetty
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Publication number: 20110211415Abstract: An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.Type: ApplicationFiled: May 9, 2011Publication date: September 1, 2011Applicant: RAMBUS INC.Inventors: Kishore Kasamsetty, Lawrence Lai, Wayne Richardson
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Patent number: 7940598Abstract: An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.Type: GrantFiled: July 22, 2008Date of Patent: May 10, 2011Assignee: Rambus Inc.Inventors: Kishore Kasamsetty, Lawrence Lai, Wayne Richardson
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Publication number: 20110055451Abstract: In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requestor IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.Type: ApplicationFiled: July 1, 2010Publication date: March 3, 2011Inventors: Frederick A. Ware, Kishore Kasamsetty
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Patent number: 7769942Abstract: In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requester IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.Type: GrantFiled: July 27, 2006Date of Patent: August 3, 2010Assignee: Rambus, Inc.Inventors: Frederick A. Ware, Kishore Kasamsetty
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Publication number: 20080279032Abstract: An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.Type: ApplicationFiled: July 22, 2008Publication date: November 13, 2008Applicant: RAMBUS INC.Inventors: Kishore Kasamsetty, Lawrence Lai, Wayne Richardson
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Patent number: 7420874Abstract: An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.Type: GrantFiled: April 6, 2005Date of Patent: September 2, 2008Assignee: Rambus Inc.Inventors: Kishore Kasamsetty, Lawrence Lai, Wayne Richardson
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Publication number: 20080028127Abstract: In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requester IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.Type: ApplicationFiled: July 27, 2006Publication date: January 31, 2008Inventors: Frederick A. Ware, Kishore Kasamsetty
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Patent number: 7136310Abstract: An integrated circuit memory device, system and method turns on an output driver in response to a stored value that represents an amount of time from when the output driver is in an operational state to when the output driver begins to output valid read data in various embodiments. An output driver outputs valid read data after a settling amount of time. The sum of the amount of time from when the memory device receives a read command to when the output driver is turned-on and the settling amount of time, is approximately the time from receiving the read command, to at least beginning to provide valid read data at the output of the integrated circuit memory device. A read command is provided to the integrated circuit memory device by a memory controller. In an embodiment, the memory controller also provides or programs the value that represents the amount of time from when the output driver is in an operational state to when the output driver begins to output valid read data.Type: GrantFiled: December 27, 2004Date of Patent: November 14, 2006Assignee: Rambus Inc.Inventor: Kishore Kasamsetty
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Publication number: 20060248305Abstract: An output-width value is stored within a configuration circuit of a memory device to control the number of output drivers that are to output data from the memory device in response to a read request. An output-latency value is determined based, at least in part, on the output-width value. The output latency value is stored within the configuration circuit to control the amount of time that transpires before the output drivers are enabled to output data in response to the read request.Type: ApplicationFiled: April 13, 2005Publication date: November 2, 2006Inventors: Wayne Fang, Kishore Kasamsetty
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Publication number: 20060227646Abstract: An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device comprises an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.Type: ApplicationFiled: April 6, 2005Publication date: October 12, 2006Inventors: Kishore Kasamsetty, Lawrence Lai, Wayne Richardson