Patents by Inventor Kishore Kasichainula

Kishore Kasichainula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210328944
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to dynamically allocate cache. An example includes a cache having a queue, data stream classification circuitry, and cache management circuitry. In an example, the data stream classification circuitry is configured to decode a data stream assigned to the queue of the cache to determine a traffic class assigned to the queue. In additional or alternative examples, the cache management circuitry is configured to, based on the traffic class assigned to the queue, allocate a portion of the cache to the queue. In some examples, the cache management circuitry is configured to transmit a signal to a memory controller to adjust allocation of the cache.
    Type: Application
    Filed: June 25, 2021
    Publication date: October 21, 2021
    Inventor: Kishore Kasichainula
  • Publication number: 20210320886
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for deterministic low latency packet forwarding for daisy chaining of network devices. An example apparatus includes fabric circuitry, first data interface circuitry and second data interface circuitry coupled to the fabric circuitry, the first data interface circuitry to, in response to a receipt of a data packet, identify the data packet to be transmitted to third data interface circuitry, a data forwarding buffer, and packet forwarding engine circuitry coupled to the data forwarding buffer and the fabric circuitry, the packet forwarding engine circuitry to store the data packet in the data forwarding buffer, and instruct the second data interface circuitry to transmit the data packet from the data forwarding buffer to the third data interface circuitry.
    Type: Application
    Filed: June 24, 2021
    Publication date: October 14, 2021
    Inventor: Kishore Kasichainula
  • Publication number: 20210266610
    Abstract: Example methods, apparatus, systems and articles of manufacture to reduce audio streaming latency between audio and Gigabit Ethernet subsystems are disclosed herein. An example integrated circuit disclosed herein to process an audio stream associated with an endpoint device on a network includes an Ethernet subsystem to access the network and an audio subsystem to process audio data associated with the audio stream. The disclosed example integrated circuit also includes a direct hardware path between the Ethernet subsystem and the audio subsystem to exchange audio data between the Ethernet subsystem and the audio subsystem without the audio data being processed by a first software driver that is to provide access to the Ethernet subsystem or a second software driver that is to provide access to the audio subsystem.
    Type: Application
    Filed: November 6, 2020
    Publication date: August 26, 2021
    Inventors: Satheesh Chellappan, Kishore Kasichainula, Frank Baehren
  • Patent number: 11057857
    Abstract: Technologies for managing internal time synchronization include an internet-of-things (IoT) device configured to determine a transport delay value as a function of a transmit path delay corresponding to a first message transmitted from an I/O device of the IoT device to a central timer of the IoT device and a receive path delay corresponding to a second message transmitted from the central timer to the I/O device. The IoT device is further configured to update, in response to having received a broadcast message from the central timer subsequent to having determined the transport delay value, a timestamp value of the received broadcast message as a function of the transport delay value. Other embodiments are described herein.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventor: Kishore Kasichainula
  • Publication number: 20210117353
    Abstract: Methods, apparatus, systems, and articles of manufacture to transmit and/or receive data streams with a network interface controller are disclosed. An example apparatus includes a direct memory access engine to fetch a descriptor for a data transmission from system memory; and determine a time to generate an interrupt based on the descriptor; a scheduler to trigger the interrupt when the time occurs, the interrupt to cause an application to sample data and store the sampled data as a payload data structure into the system memory; the direct memory access engine to access the payload data structure from the system memory; and the scheduler to cause transmission of the payload data structure.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 22, 2021
    Inventors: Kishore Kasichainula, Boon Leong Ong
  • Publication number: 20210097019
    Abstract: The present disclosure generally relates to a device, method, or system for time sensitive networking. In an example, the device can include a time-sensitive networking controller and a scheduler. The device also includes an enhanced gate control list maintained on the time-sensitive networking controller to include a direct memory access address, a launch time, and a pre-fetch time for a data packet. The device may also include a transmitter of the time-sensitive networking controller to transmit the data packet retrieved using the direct memory access address at the launch time identified by the scheduler.
    Type: Application
    Filed: August 24, 2020
    Publication date: April 1, 2021
    Inventor: Kishore Kasichainula
  • Publication number: 20210014177
    Abstract: In one embodiment, a network interface controller (NIC) includes multiple packet transmission queues to queue data packets for transmission. The data packets are assigned to multiple traffic classes. The NIC also includes multiple input/output (I/O) interfaces for retrieving the data packets from memory. Each I/O interface is assigned to a subset of the traffic classes. The NIC also includes scheduler circuitry to select a first data packet to be retrieved from memory, and direct memory access (DMA) engine circuitry to retrieve the first data packet from memory via one of the I/O interfaces based on the traffic class of the first data packet, and store the first data packet in one of the packet transmission queues. The NIC also includes a transmission interface to transmit the first data packet over a network at a corresponding launch time indicated by the scheduler circuitry.
    Type: Application
    Filed: September 26, 2020
    Publication date: January 14, 2021
    Applicant: Intel Corporation
    Inventor: Kishore Kasichainula
  • Patent number: 10834434
    Abstract: Example methods, apparatus, systems and articles of manufacture to reduce audio streaming latency between audio and Gigabit Ethernet subsystems are disclosed herein. An example integrated circuit disclosed herein to process an audio stream associated with an endpoint device on a network includes an Ethernet subsystem to access the network and an audio subsystem to process audio data associated with the audio stream. The disclosed example integrated circuit also includes a direct hardware path between the Ethernet subsystem and the audio subsystem to exchange audio data between the Ethernet subsystem and the audio subsystem without the audio data being processed by a first software driver that is to provide access to the Ethernet subsystem or a second software driver that is to provide access to the audio subsystem.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: November 10, 2020
    Assignee: Intel Corporation
    Inventors: Satheesh Chellappan, Kishore Kasichainula, Frank Baehren
  • Patent number: 10788533
    Abstract: Technology for bypass testing of an integrated circuit using a testing device. The testing device comprising a port configured to connect to an integrated circuit before the integrated circuit is packaged into an end product. The testing device further comprising a controller with architecture configured to bypass a training process designed to be initiated when the integrated circuit is first connected to the port and the port is powered on, confirm a connection between the integrated circuit and the testing device, send a test pattern to the integrated circuit to execute; and receive results from the integrated circuit executing the test pattern.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Kishore Kasichainula, Satheesh Chellappan, Lay Chen Ong, Harish G. Kamat
  • Patent number: 10754816
    Abstract: The present disclosure generally relates to a device, method, or system for time sensitive networking. In an example, the device can include a time-sensitive networking controller and a scheduler. The device also includes an enhanced gate control list maintained on the time-sensitive networking controller to include a direct memory access address, a launch time, and a pre-fetch time for a data packet. The device may also include a transmitter of the time-sensitive networking controller to transmit the data packet retrieved using the direct memory access address at the launch time identified by the scheduler.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventor: Kishore Kasichainula
  • Patent number: 10606772
    Abstract: In one example a Universal Serial Bus (USB) controller comprises at least one memory register to store one or more enumeration parameters for a USB connection with the USB controller and logic, at least partially including hardware logic, to detect a USB connection with a remote device via the USB connection, retrieve one or more connection enumeration parameters for the USB connection from the at least one memory register on the USB host controller, and implement a connection enumeration process using the one or more connection enumeration parameters retrieved from the memory register on the USB controller. Other examples may be described.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: March 31, 2020
    Assignee: INTEL CORPORATION
    Inventors: Satheesh Chellappan, Kishore Kasichainula, Lay Cheng Ong, Chee Lim Poon, Harish G. Kamat
  • Publication number: 20190158890
    Abstract: Example methods, apparatus, systems and articles of manufacture to reduce audio streaming latency between audio and Gigabit Ethernet subsystems are disclosed herein. An example integrated circuit disclosed herein to process an audio stream associated with an endpoint device on a network includes an Ethernet subsystem to access the network and an audio subsystem to process audio data associated with the audio stream. The disclosed example integrated circuit also includes a direct hardware path between the Ethernet subsystem and the audio subsystem to exchange audio data between the Ethernet subsystem and the audio subsystem without the audio data being processed by a first software driver that is to provide access to the Ethernet subsystem or a second software driver that is to provide access to the audio subsystem.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 23, 2019
    Inventors: Satheesh Chellappan, Kishore Kasichainula, Frank Baehren
  • Publication number: 20190121781
    Abstract: The present disclosure generally relates to a device, method, or system for time sensitive networking. In an example, the device can include a time-sensitive networking controller and a scheduler. The device also includes an enhanced gate control list maintained on the time-sensitive networking controller to include a direct memory access address, a launch time, and a pre-fetch time for a data packet. The device may also include a transmitter of the time-sensitive networking controller to transmit the data packet retrieved using the direct memory access address at the launch time identified by the scheduler.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 25, 2019
    Applicant: INTEL CORPORATION
    Inventor: Kishore Kasichainula
  • Publication number: 20190101592
    Abstract: Technology for bypass testing of an integrated circuit using a testing device. The testing device comprising a port configured to connect to an integrated circuit before the integrated circuit is packaged into an end product. The testing device further comprising a controller with architecture configured to bypass a training process designed to be initiated when the integrated circuit is first connected to the port and the port is powered on, confirm a connection between the integrated circuit and the testing device, send a test pattern to the integrated circuit to execute; and receive results from the integrated circuit executing the test pattern.
    Type: Application
    Filed: August 29, 2018
    Publication date: April 4, 2019
    Applicant: Intel Corporation
    Inventors: Kishore Kasichainula, Satheesh Chellappan, Lay Chen Ong, Harish G. Kamat
  • Publication number: 20190045475
    Abstract: Technologies for managing internal time synchronization include an internet-of-things (IoT) device configured to determine a transport delay value as a function of a transmit path delay corresponding to a first message transmitted from an I/O device of the IoT device to a central timer of the IoT device and a receive path delay corresponding to a second message transmitted from the central timer to the I/O device. The IoT device is further configured to update, in response to having received a broadcast message from the central timer subsequent to having determined the transport delay value, a timestamp value of the received broadcast message as a function of the transport delay value. Other embodiments are described herein.
    Type: Application
    Filed: September 28, 2018
    Publication date: February 7, 2019
    Inventor: Kishore Kasichainula
  • Publication number: 20190018802
    Abstract: In one example a Universal Serial Bus (USB) controller comprises at least one memory register to store one or more enumeration parameters for a USB connection with the USB controller and logic, at least partially including hardware logic, to detect a USB connection with a remote device via the USB connection, retrieve one or more connection enumeration parameters for the USB connection from the at least one memory register on the USB host controller, and implement a connection enumeration process using the one or more connection enumeration parameters retrieved from the memory register on the USB controller. Other examples may be described.
    Type: Application
    Filed: April 17, 2018
    Publication date: January 17, 2019
    Applicant: Intel Corporation
    Inventors: SATHEESH CHELLAPPAN, KISHORE KASICHAINULA, LAY CHENG ONG, CHEE LIM POON, HARISH G. KAMAT
  • Patent number: 10122484
    Abstract: Technologies for internal time synchronization in a compute device are disclosed. A timestamp value from an always running timer in the compute device may be broadcast using a serial broadcast wire to other components of the compute device, such as a network interface card. The network interface card may keep a local always running timer that mirrors the always running timer and synchronized to the always running timer by monitoring the serial broadcast wire. The network interface card may take a snapshot of both a system timer on the network interface card and the local always running timer. The network interface card may oversample the local always running timer in order to capture a more precise snapshot of the local always running timer.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventor: Kishore Kasichainula
  • Patent number: 8432731
    Abstract: A method, system, and apparatus magnetically coupled electrostatically shiftable memory device and method are disclosed. In one embodiment, a method includes electrostatically decoupling a separate structure and a surface that are magnetically coupled (e.g., an electrostatic force to decouple the separate structure and the surface is generated with an electrode), shifting the separate structure between the surface and a other surface with the electrostatic force (e.g., shifting the separate structure moves the entire separate structure), and magnetically coupling the separate structure to the other surface.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: April 30, 2013
    Inventors: Sridhar Kasichainula, Kishore Kasichainula, Mike Daneman
  • Publication number: 20120051128
    Abstract: A method, system, and apparatus magnetically coupled electrostatically shiftable memory device and method are disclosed. In one embodiment, a method includes electrostatically decoupling a separate structure and a surface that are magnetically coupled (e.g., an electrostatic force to decouple the separate structure and the surface is generated with an electrode), shifting the separate structure between the surface and a other surface with the electrostatic force (e.g., shifting the separate structure moves the entire separate structure), and magnetically coupling the separate structure to the other surface.
    Type: Application
    Filed: September 29, 2008
    Publication date: March 1, 2012
    Inventors: SRIDHAR KASICHAINULA, Kishore Kasichainula, Mike Daneman